From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Add device tree nodes for the USB3.1 controller on the Agilex5 SoC
and enable it on the SoCDK board. The USB3.1 block consists of a
SoC-specific wrapper around the Synopsys DWC3 core that handles clock,
reset, and address translation configuration.
The DWC3 core is described as a child of the wrapper to reflect the
hardware hierarchy and comply with the DWC3 binding requirements.
This commit also disables the DWC2 USB controller node, as the daughter
card does not support simultaneous operation of both USB controllers.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 +++++++++++++++++++
.../boot/dts/intel/socfpga_agilex5_socdk.dts | 9 ++++++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a22cf6a211e2..6253bda0e819 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -444,6 +444,30 @@ usb0: usb@10b00000 {
status = "disabled";
};
+ usb31: usb1@11000000 {
+ compatible = "altr,agilex5-dwc3";
+ reg = <0x11000000 0x100000>;
+ ranges = <0x0 0x11000000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+ <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
+ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+
+ dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu 7>;
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&usbphy0>, <&usbphy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
watchdog0: watchdog@10d00200 {
compatible = "snps,dw-wdt";
reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..af301191b262 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -103,10 +103,17 @@ &uart0 {
};
&usb0 {
- status = "okay";
disable-over-current;
};
+&usb31 {
+ status = "okay";
+};
+
+&dwc3 {
+ dr_mode = "host";
+};
+
&watchdog0 {
status = "okay";
};
--
2.49.GIT