From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add device tree nodes for the USB3.1 controller on the Agilex5 SoC
and enable it on the SoCDK board. The USB3.1 block consists of a
SoC-specific wrapper around the Synopsys DWC3 core that handles clock,
reset, and address translation configuration.

The DWC3 core is described as a child of the wrapper to reflect the
hardware hierarchy and comply with the DWC3 binding requirements.

This commit also disables the DWC2 USB controller node, as the daughter
card does not support simultaneous operation of both USB controllers.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++++++-
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a22cf6a211e2..6253bda0e819 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -444,6 +444,30 @@ usb0: usb@10b00000 {
 			status = "disabled";
 		};
 
+		usb31: usb1@11000000 {
+			compatible = "altr,agilex5-dwc3";
+			reg = <0x11000000 0x100000>;
+			ranges = <0x0 0x11000000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+				<&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
+			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+
+			dwc3: usb@0 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x10000>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&smmu 7>;
+				dr_mode = "host";
+				maximum-speed = "super-speed";
+				phys = <&usbphy0>, <&usbphy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
 		watchdog0: watchdog@10d00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..af301191b262 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -103,10 +103,17 @@ &uart0 {
 };
 
 &usb0 {
-	status = "okay";
 	disable-over-current;
 };
 
+&usb31 {
+	status = "okay";
+};
+
+&dwc3 {
+	dr_mode = "host";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.49.GIT

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on usb/usb-testing]
[also build test ERROR on usb/usb-next usb/usb-linus robh/for-next westeri-thunderbolt/next linus/master v6.18-rc5 next-20251113]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/adrianhoyin-ng-altera-com/dt-bindings-usb-dwc3-altera-Add-binding-for-Altera-DWC3-wrapper/20251111-142609
base:   https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing
patch link:    https://lore.kernel.org/r/7ec6e1787a677f6614f7f991a31a9ac58b539780.1762839776.git.adrianhoyin.ng%40altera.com
patch subject: [PATCH 2/4] arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK
config: arm64-randconfig-002-20251113 (https://download.01.org/0day-ci/archive/20251114/202511141429.Ae8oNWSX-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 0bba1e76581bad04e7d7f09f5115ae5e2989e0d9)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251114/202511141429.Ae8oNWSX-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511141429.Ae8oNWSX-lkp@intel.com/

All errors (new ones prefixed by >>):

   also defined at arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts:111.7-113.3
>> ERROR: Input tree has errors, aborting (use -f to force output)
--
>> ERROR: Input tree has errors, aborting (use -f to force output)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

On Tue, Nov 11, 2025 at 02:18:46PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add device tree nodes for the USB3.1 controller on the Agilex5 SoC
> and enable it on the SoCDK board. The USB3.1 block consists of a
> SoC-specific wrapper around the Synopsys DWC3 core that handles clock,
> reset, and address translation configuration.
> 
> The DWC3 core is described as a child of the wrapper to reflect the
> hardware hierarchy and comply with the DWC3 binding requirements.
> 
> This commit also disables the DWC2 USB controller node, as the daughter
> card does not support simultaneous operation of both USB controllers.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 +++++++++++++++++++
>  .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++++++-

DTS cannot be mixed here. You are targetting USB, so you cannot mix up
other subsystems.

Best regards,
Krzysztof