From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add a device tree binding document for the Altera wrapper around the
Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
SoC-specific integration such as clock and reset control for the USB
subsystem.

A parent–child node structure is used to comply with the generic DWC3
binding, which restricts the core node to a single clock and reset.
The wrapper node provides the additional clocks, resets, and address
translation required for the Agilex5 integration.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml

diff --git a/Documentation/devicetree/bindings/usb/dwc3-altera.yaml b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
new file mode 100644
index 000000000000..c998d587723d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/dwc3-altera.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera DWC3 USB Controller Wrapper
+
+maintainers:
+  - Adrian Ng <adrianhoyin.ng@altera.com>
+
+description: |
+  The Altera SoCFPGA wrapper around the Synopsys DesignWare USB3 (DWC3) core.
+  The wrapper provides SoC-specific integration such as reset and clock control.
+
+properties:
+  compatible:
+    const: altr,agilex5-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    minItems: 1
+    maxItems: 2
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+
+required:
+  - compatible
+  - reg
+  - ranges
+  - clocks
+  - resets
+
+patternProperties:
+  "^usb(@[0-9a-f]+)?$":
+    type: object
+    $ref: /schemas/usb/snps,dwc3.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    usb@11000000 {
+        compatible = "altr,agilex5-dwc3";
+        reg = <0x11000000 0x100000>;
+        ranges = <0x0 0x11000000 0x100000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        clocks = <&clkmgr 54>, <&clkmgr 55>;
+        resets = <&rst 36>, <&rst 44>;
+
+        dwc3: usb@0 {
+            compatible = "snps,dwc3";
+            reg = <0x0 0x100000>;
+            interrupts = <0 94 4>;
+            iommus = <&smmu 7>;
+            phys = <&usbphy0>, <&usbphy0>;
+            phy-names = "usb2-phy", "usb3-phy";
+            dr_mode = "host";
+            maximum-speed = "super-speed";
+            snps,dis_u2_susphy_quirk;
+            snps,dis_u3_susphy_quirk;
+            status = "okay";
+        };
+    };
+...
-- 
2.49.GIT

On Tue, Nov 11, 2025 at 02:18:45PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add a device tree binding document for the Altera wrapper around the
> Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
> SoC-specific integration such as clock and reset control for the USB
> subsystem.
> 
> A parent–child node structure is used to comply with the generic DWC3

No, that's long time legacy. Use single node.

> binding, which restricts the core node to a single clock and reset.
> The wrapper node provides the additional clocks, resets, and address
> translation required for the Agilex5 integration.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-altera.yaml b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
> new file mode 100644
> index 000000000000..c998d587723d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml

Filename matching compatible.

> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/dwc3-altera.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera DWC3 USB Controller Wrapper
> +
> +maintainers:
> +  - Adrian Ng <adrianhoyin.ng@altera.com>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The Altera SoCFPGA wrapper around the Synopsys DesignWare USB3 (DWC3) core.
> +  The wrapper provides SoC-specific integration such as reset and clock control.
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2

No, this cannot be flexible. Please do not write bindings completely
different than everything else.

List the items, fix size/length of the array.

> +
> +  resets:
> +    minItems: 1
> +    maxItems: 2

Same problem,

> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1

No. Use single node.

> +
> +  ranges: true

Drop

> +
> +required:
> +  - compatible
> +  - reg
> +  - ranges
> +  - clocks
> +  - resets
> +
> +patternProperties:
> +  "^usb(@[0-9a-f]+)?$":
> +    type: object
> +    $ref: /schemas/usb/snps,dwc3.yaml#

Drop

> +
> +unevaluatedProperties: false

That's wrong in this context. Please read example-schema or writing
schema.

> +
> +examples:
> +  - |
> +    usb@11000000 {
> +        compatible = "altr,agilex5-dwc3";
> +        reg = <0x11000000 0x100000>;
> +        ranges = <0x0 0x11000000 0x100000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        clocks = <&clkmgr 54>, <&clkmgr 55>;
> +        resets = <&rst 36>, <&rst 44>;
> +
> +        dwc3: usb@0 {
> +            compatible = "snps,dwc3";
> +            reg = <0x0 0x100000>;
> +            interrupts = <0 94 4>;

We don't use such code... Look at any decent DTS.

> +            iommus = <&smmu 7>;
> +            phys = <&usbphy0>, <&usbphy0>;
> +            phy-names = "usb2-phy", "usb3-phy";
> +            dr_mode = "host";
> +            maximum-speed = "super-speed";
> +            snps,dis_u2_susphy_quirk;
> +            snps,dis_u3_susphy_quirk;
> +            status = "okay";

Drop

This is a pretty poor binding. You just repeat basic mistakes, fixed in
other NEW bindings. Last time few-line patch, with obvious issues, had
two reviewed-by from Altera. This one - bigger patch - no one cared to
review?

Best regards,
Krzysztof

On Tue, Nov 11, 2025 at 02:18:45PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add a device tree binding document for the Altera wrapper around the
> Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
> SoC-specific integration such as clock and reset control for the USB
> subsystem.
> 
> A parent–child node structure is used to comply with the generic DWC3
> binding, which restricts the core node to a single clock and reset.
> The wrapper node provides the additional clocks, resets, and address
> translation required for the Agilex5 integration.

Also, standard message:

A nit, subject: drop second/last, redundant "binding for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

Best regards,
Krzysztof