From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

This patch series adds USB3.1 support for the Altera Agilex5 SoCFPGA
platform. The integration is based on the Synopsys DesignWare USB3
(DWC3) controller, wrapped by an Altera-specific layer that manages
clocks, resets, and other SoC-level interfaces.

The series introduces a new device tree binding for the Altera DWC3
wrapper, adds the corresponding device tree nodes for Agilex5 and its
SoCDK board, enables support for the new compatible in the dwc3-of-simple
driver, and extends the DWC3 core to handle configurable DMA addressable
bits. This allows Agilex5, which uses a 40-bit DMA address space, to
function correctly with SMMU-enabled systems.

This series also disables the DWC2 USB controller node, as the daughter
card does not support simultaneous operation of both USB controllers.

Adrian Ng Ho Yin (4):
  dt-bindings: usb: dwc3-altera: Add binding for Altera DWC3 wrapper
  arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK
  usb: dwc3: of-simple: Add support for Agilex5 SoCFPGA
  usb: dwc3: add support for configurable DMA addressable bits

 .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 ++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++-
 drivers/usb/dwc3/core.c                       |  9 ++-
 drivers/usb/dwc3/core.h                       |  3 +
 drivers/usb/dwc3/dwc3-of-simple.c             |  1 +
 6 files changed, 122 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml

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2.49.GIT