Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and references a
reserved memory region used for communication with the Secure Device
Manager (SDM).
Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations, particularly with the addition of
IOMMU support. Unlike earlier platforms, Agilex5 enables the use of the
Translation Buffer Unit (TBU) in non-secure mode, allowing Linux to access
it through the IOMMU framework. This commit updates the device tree
structure to support Agilex5-specific handling of the SVC interface,
including the necessary bindings for IOMMU integration.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v4:
- Exclude peers reviewers in the sign off.
Changes in v3:
- include iommu property in svc node.
- Rephrase git commit message to describe iommu presence
in Agilex5
Changes in v2:
- Rephrase commit message to exclude mentioning iommu
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a13ccee3c4c3..15284092897e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -841,5 +841,14 @@ queue7 {
};
};
};
+
+ firmware {
+ svc {
+ compatible = "intel,agilex5-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+ iommus = <&smmu 10>;
+ };
+ };
};
};
--
2.43.7