Add support for standard tx-internal-delay-ps and rx-internal-delay-ps
properties on port nodes to allow fine-tuning of RGMII clock delays.

The GSWIP switch hardware supports delay values in 500 picosecond
increments from 0 to 3500 picoseconds, with a default of 2000
picoseconds for both TX and RX delays.

This corresponds to the driver changes that allow adjusting MII delays
using Device Tree properties instead of relying solely on the PHY
interface mode.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
 .../bindings/net/dsa/lantiq,gswip.yaml        | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
index f3154b19af78..ed274bfb8d49 100644
--- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
@@ -8,6 +8,24 @@ title: Lantiq GSWIP Ethernet switches
 
 allOf:
   - $ref: dsa.yaml#/$defs/ethernet-ports
+  - properties:
+      ports:
+        patternProperties:
+          "^port@[0-6]$":
+            type: object
+            properties:
+              tx-internal-delay-ps:
+                enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
+                default: 2000
+                description:
+                  RGMII TX Clock Delay defined in pico seconds.
+                  The delay lines adjust the MII clock vs. data timing.
+              rx-internal-delay-ps:
+                enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
+                default: 2000
+                description:
+                  RGMII RX Clock Delay defined in pico seconds.
+                  The delay lines adjust the MII clock vs. data timing.
 
 maintainers:
   - Hauke Mehrtens <hauke@hauke-m.de>
@@ -115,6 +133,8 @@ examples:
                             label = "lan3";
                             phy-mode = "rgmii";
                             phy-handle = <&phy0>;
+                            tx-internal-delay-ps = <2000>;
+                            rx-internal-delay-ps = <2000>;
                     };
 
                     port@1 {
-- 
2.51.0

Hi Daniel,

On 25/10/2025 16:49, Daniel Golle wrote:
> Add support for standard tx-internal-delay-ps and rx-internal-delay-ps
> properties on port nodes to allow fine-tuning of RGMII clock delays.
> 
> The GSWIP switch hardware supports delay values in 500 picosecond
> increments from 0 to 3500 picoseconds, with a default of 2000
> picoseconds for both TX and RX delays.
> 
> This corresponds to the driver changes that allow adjusting MII delays
> using Device Tree properties instead of relying solely on the PHY
> interface mode.
> 
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
>  .../bindings/net/dsa/lantiq,gswip.yaml        | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
> index f3154b19af78..ed274bfb8d49 100644
> --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
> +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
> @@ -8,6 +8,24 @@ title: Lantiq GSWIP Ethernet switches
>  
>  allOf:
>    - $ref: dsa.yaml#/$defs/ethernet-ports
> +  - properties:
> +      ports:
> +        patternProperties:
> +          "^port@[0-6]$":
> +            type: object
> +            properties:
> +              tx-internal-delay-ps:
> +                enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
> +                default: 2000
> +                description:
> +                  RGMII TX Clock Delay defined in pico seconds.
> +                  The delay lines adjust the MII clock vs. data timing.
> +              rx-internal-delay-ps:
> +                enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
> +                default: 2000
> +                description:
> +                  RGMII RX Clock Delay defined in pico seconds.
> +                  The delay lines adjust the MII clock vs. data timing.
>  
>  maintainers:
>    - Hauke Mehrtens <hauke@hauke-m.de>
> @@ -115,6 +133,8 @@ examples:
>                              label = "lan3";
>                              phy-mode = "rgmii";
>                              phy-handle = <&phy0>;
> +                            tx-internal-delay-ps = <2000>;
> +                            rx-internal-delay-ps = <2000>;

I guess that in this example, with a 2ns delay, this is no longer
"rgmii" but "rgmii-id", as delays are inserted by the switch. It would
make sense to update the phy-mode.

>                      };
>  
>                      port@1 {

Maxime