ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a
PGA (programmable gain amplifier) that scales the input signal prior to it
reaching the ADC inputs. The PGA is controlled through a couple of pins (A0
and A1) that set one of four possible signal gain configurations.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4
- Now only documenting GPIO setup to control ADAQ PGA pins.
Pin strapped/hardwired connections to PGA pins may benefit from a "fixed-gpios"
driver which may (or may not?) use the shared GPIO abstraction layer [1]. I may
propose support for pin-strapped/hardwired connections when I get a working
fixed-gpios implementation.
[1]: https://lore.kernel.org/linux-gpio/CAMRc=Mdb_cUG+hKq8GyfUP1SYBh0p19J+4dFG7G3JSuZTr4n8Q@mail.gmail.com/T/#t
.../bindings/iio/adc/adi,ad4030.yaml | 71 +++++++++++++++++--
1 file changed, 66 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
index 564b6f67a96e..d0e8452598d4 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
@@ -19,6 +19,8 @@ description: |
* https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24-4032-24.pdf
* https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-24_ad4632-24.pdf
* https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-16-4632-16.pdf
+ * https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4216.pdf
+ * https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4224.pdf
$ref: /schemas/spi/spi-peripheral-props.yaml#
@@ -31,6 +33,8 @@ properties:
- adi,ad4630-24
- adi,ad4632-16
- adi,ad4632-24
+ - adi,adaq4216
+ - adi,adaq4224
reg:
maxItems: 1
@@ -54,6 +58,14 @@ properties:
description:
Internal buffered Reference. Used when ref-supply is not connected.
+ vddh-supply:
+ description:
+ PGIA Positive Power Supply.
+
+ vdd-fda-supply:
+ description:
+ FDA Positive Power Supply.
+
cnv-gpios:
description:
The Convert Input (CNV). It initiates the sampling conversions.
@@ -64,6 +76,13 @@ properties:
The Reset Input (/RST). Used for asynchronous device reset.
maxItems: 1
+ pga-gpios:
+ description:
+ A0 and A1 pins for gain selection. For devices that have PGA configuration
+ input pins, pga-gpios should be defined.
+ minItems: 2
+ maxItems: 2
+
pwms:
description: PWM signal connected to the CNV pin.
maxItems: 1
@@ -86,11 +105,30 @@ required:
- vio-supply
- cnv-gpios
-oneOf:
- - required:
- - ref-supply
- - required:
- - refin-supply
+allOf:
+ - oneOf:
+ - required:
+ - ref-supply
+ - required:
+ - refin-supply
+ # ADAQ devices require a gain property to indicate how hardware PGA is set
+ - if:
+ properties:
+ compatible:
+ contains:
+ pattern: ^adi,adaq
+ then:
+ required:
+ - vddh-supply
+ - vdd-fda-supply
+ - pga-gpios
+ properties:
+ ref-supply: false
+ else:
+ properties:
+ adi,pga-value: false
+ pga-gpios: false
+
unevaluatedProperties: false
@@ -114,3 +152,26 @@ examples:
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,adaq4216";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ vdd-5v-supply = <&supply_5V>;
+ vdd-1v8-supply = <&supply_1_8V>;
+ vio-supply = <&supply_1_8V>;
+ refin-supply = <&refin_sup>;
+ vddh-supply = <&vddh>;
+ vdd-fda-supply = <&vdd_fda>;
+ cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ pga-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>,
+ <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+...
--
2.39.2On Wed, 8 Oct 2025 10:51:37 -0300 Marcelo Schmitt <marcelo.schmitt@analog.com> wrote: > ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a > PGA (programmable gain amplifier) that scales the input signal prior to it > reaching the ADC inputs. The PGA is controlled through a couple of pins (A0 > and A1) that set one of four possible signal gain configurations. > > Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> > --- > Change log v3 -> v4 > - Now only documenting GPIO setup to control ADAQ PGA pins. A comment on a change log is my only contribution to review of this version (I didn't have anything else to say!) Fully agree on separating that issue out. When we do implement it I 'hope' that whatever we/you come up with there can be generic enough that at most we'd just using it an extra example for this binding. I.e. I'd expect it to be mostly documented somewhere generic. I liked the detailed explanation later in the thread btw. Jonathan
On Wed, Oct 08, 2025 at 10:51:37AM -0300, Marcelo Schmitt wrote:
> ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a
> PGA (programmable gain amplifier) that scales the input signal prior to it
> reaching the ADC inputs. The PGA is controlled through a couple of pins (A0
> and A1) that set one of four possible signal gain configurations.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
> Change log v3 -> v4
> - Now only documenting GPIO setup to control ADAQ PGA pins.
>
> Pin strapped/hardwired connections to PGA pins may benefit from a "fixed-gpios"
> driver which may (or may not?) use the shared GPIO abstraction layer [1]. I may
> propose support for pin-strapped/hardwired connections when I get a working
> fixed-gpios implementation.
What is a "fixed-gpio" as compared to a hog, from a dt point of view?
Is it purely a software change?
This looks fine other than the potential oversight I pointed out in the
other mail.
Cheers,
COnor
>
> [1]: https://lore.kernel.org/linux-gpio/CAMRc=Mdb_cUG+hKq8GyfUP1SYBh0p19J+4dFG7G3JSuZTr4n8Q@mail.gmail.com/T/#t
>
> .../bindings/iio/adc/adi,ad4030.yaml | 71 +++++++++++++++++--
> 1 file changed, 66 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
> index 564b6f67a96e..d0e8452598d4 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
> @@ -19,6 +19,8 @@ description: |
> * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24-4032-24.pdf
> * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-24_ad4632-24.pdf
> * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-16-4632-16.pdf
> + * https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4216.pdf
> + * https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4224.pdf
>
> $ref: /schemas/spi/spi-peripheral-props.yaml#
>
> @@ -31,6 +33,8 @@ properties:
> - adi,ad4630-24
> - adi,ad4632-16
> - adi,ad4632-24
> + - adi,adaq4216
> + - adi,adaq4224
>
> reg:
> maxItems: 1
> @@ -54,6 +58,14 @@ properties:
> description:
> Internal buffered Reference. Used when ref-supply is not connected.
>
> + vddh-supply:
> + description:
> + PGIA Positive Power Supply.
> +
> + vdd-fda-supply:
> + description:
> + FDA Positive Power Supply.
> +
> cnv-gpios:
> description:
> The Convert Input (CNV). It initiates the sampling conversions.
> @@ -64,6 +76,13 @@ properties:
> The Reset Input (/RST). Used for asynchronous device reset.
> maxItems: 1
>
> + pga-gpios:
> + description:
> + A0 and A1 pins for gain selection. For devices that have PGA configuration
> + input pins, pga-gpios should be defined.
> + minItems: 2
> + maxItems: 2
> +
> pwms:
> description: PWM signal connected to the CNV pin.
> maxItems: 1
> @@ -86,11 +105,30 @@ required:
> - vio-supply
> - cnv-gpios
>
> -oneOf:
> - - required:
> - - ref-supply
> - - required:
> - - refin-supply
> +allOf:
> + - oneOf:
> + - required:
> + - ref-supply
> + - required:
> + - refin-supply
> + # ADAQ devices require a gain property to indicate how hardware PGA is set
> + - if:
> + properties:
> + compatible:
> + contains:
> + pattern: ^adi,adaq
> + then:
> + required:
> + - vddh-supply
> + - vdd-fda-supply
> + - pga-gpios
> + properties:
> + ref-supply: false
> + else:
> + properties:
> + adi,pga-value: false
> + pga-gpios: false
> +
>
> unevaluatedProperties: false
>
> @@ -114,3 +152,26 @@ examples:
> reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
> };
> };
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + adc@0 {
> + compatible = "adi,adaq4216";
> + reg = <0>;
> + spi-max-frequency = <80000000>;
> + vdd-5v-supply = <&supply_5V>;
> + vdd-1v8-supply = <&supply_1_8V>;
> + vio-supply = <&supply_1_8V>;
> + refin-supply = <&refin_sup>;
> + vddh-supply = <&vddh>;
> + vdd-fda-supply = <&vdd_fda>;
> + cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
> + pga-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>,
> + <&gpio0 3 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +...
> --
> 2.39.2
>
On 10/08, Conor Dooley wrote:
> On Wed, Oct 08, 2025 at 10:51:37AM -0300, Marcelo Schmitt wrote:
> > ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a
> > PGA (programmable gain amplifier) that scales the input signal prior to it
> > reaching the ADC inputs. The PGA is controlled through a couple of pins (A0
> > and A1) that set one of four possible signal gain configurations.
> >
> > Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> > ---
> > Change log v3 -> v4
> > - Now only documenting GPIO setup to control ADAQ PGA pins.
> >
> > Pin strapped/hardwired connections to PGA pins may benefit from a "fixed-gpios"
> > driver which may (or may not?) use the shared GPIO abstraction layer [1]. I may
> > propose support for pin-strapped/hardwired connections when I get a working
> > fixed-gpios implementation.
>
> What is a "fixed-gpio" as compared to a hog, from a dt point of view?
> Is it purely a software change?
Short answer:
I think "fixed-gpio" and gpio-hog would mean the same from dt point of view.
Yes, it's mainly related to software.
Long answer:
We would like to read the state of a pin from the GPIO client driver. Maybe we
are already able to read gpio-hog states from client drivers and just didn't
find out how.
The idea is to standardize and simplify the dt bindings when peripheral pins can
either be connected GPIOs or hard-wired to some logic level.
For the particular example of ADAQ4216, it can have PGA control pins connected
to GPIOs.
+-------------+ +-------------+
| ADC | | HOST |
| | | |
| SPI lines |<=======>| SPI lines |
| | | |
| A0 |<--------| GPIO_A |
| A1 |<--------| GPIO_B |
+-------------+ +-------------+
But the pins might instead be hard-wired, like
+-------------+ +-------------+
| ADC | | HOST |
| | | |
| SPI lines |<=======>| SPI lines |
| | +-------------+
| A0 |<-----+
| A1 |<-----+
+-------------+ |
VIO
or
+-------------+ +-------------+
| ADC | | HOST |
| | | |
| SPI lines |<=======>| SPI lines |
| | +-------------+
| A0 |<--------- VIO
| A1 |<-----+
+-------------+ |
GND
Or even, possibly, a mix of GPIO and hard-wired.
+-------------+ +-------------+
| ADC | | HOST |
| | | |
| SPI lines |<=======>| SPI lines |
| | | |
| A0 |<--------| GPIO_A |
| | +-------------+
| A1 |<-----+
+-------------+ |
GND
We have bindings (like adi,ad7191.yaml [1]) describing the hard-wired setups
with function specific properties. E.g.
adi,pga-value:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Should be present if PGA pins are pin-strapped. Possible values:
Gain 1 (PGA1=0, PGA2=0)
Gain 8 (PGA1=0, PGA2=1)
Gain 64 (PGA1=1, PGA2=0)
Gain 128 (PGA1=1, PGA2=1)
If defined, pga-gpios must be absent.
enum: [1, 8, 64, 128]
This approach works fine, but it requires documenting device-specific values
(e.g. gain 1, gain 8, ..., gain X) for each new series of ADCs because each
each series has different hardware properties.
Sometimes peripherals have pins with different functions that are also either
hard-wired or connected to GPIOs (like adi,ad7606.yaml [2] and adi,ad7625.yaml [3]).
Software wants to know about the state of those pins. When they are connected
to GPIOs, we can just read the GPIO value. But when the pins are hard-wired,
we have to set additional dt properties (e.g. adi,pga-value) and then software
figures out the state of the pins from the value read from dt.
What we wonder is whether it would be possible to have both the GPIO and
hard-wired cases described by gpio properties.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml#n77
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml#n127
[3]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7625.yaml#n70
For example, instead of having
/* All GPIOs case */
pga-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>;
and
/* All hard-wired (pin-strapped) case */
adi,pga-value = <1>;
maybe we could have something like
/* All gpios */
pga-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>,
<&gpio0 1 GPIO_ACTIVE_HIGH>;
/* or all hard-wired */
pga-gpios = <&fixed_gpio GPIO_FIXED_LOW>,
<&fixed_gpio GPIO_FIXED_LOW>;
as suggested by David [4].
Though, I'm also a bit worried about such way of describing the hard-wired
connections being potentially confusing as those "fixed-gpios" would not
necessarily mean any actual GPIO.
[4]: https://lore.kernel.org/linux-iio/CAMknhBHzXLjkbKAjkgRwEps=0YrOgUcdvRpuPRrcPkwfwWo88w@mail.gmail.com/
With best regards,
Marcelo
On Thu, Oct 09, 2025 at 07:02:31PM -0300, Marcelo Schmitt wrote: > On 10/08, Conor Dooley wrote: > > On Wed, Oct 08, 2025 at 10:51:37AM -0300, Marcelo Schmitt wrote: > > > ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a > > > PGA (programmable gain amplifier) that scales the input signal prior to it > > > reaching the ADC inputs. The PGA is controlled through a couple of pins (A0 > > > and A1) that set one of four possible signal gain configurations. > > > > > > Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> > > > --- > > > Change log v3 -> v4 > > > - Now only documenting GPIO setup to control ADAQ PGA pins. > > > > > > Pin strapped/hardwired connections to PGA pins may benefit from a "fixed-gpios" > > > driver which may (or may not?) use the shared GPIO abstraction layer [1]. I may > > > propose support for pin-strapped/hardwired connections when I get a working > > > fixed-gpios implementation. > > > > What is a "fixed-gpio" as compared to a hog, from a dt point of view? > > Is it purely a software change? > > > Short answer: > > I think "fixed-gpio" and gpio-hog would mean the same from dt point of view. > Yes, it's mainly related to software. Long answer is wasted on me, what you I just wanted to know if you were proposing something new on the dt side or just able to use hogs :) Well, wasted in an official capacity, obviously new features in the kernel are also interesting to learn about. Cheers, Conor. > > > Long answer: > > We would like to read the state of a pin from the GPIO client driver. Maybe we > are already able to read gpio-hog states from client drivers and just didn't > find out how. > > The idea is to standardize and simplify the dt bindings when peripheral pins can > either be connected GPIOs or hard-wired to some logic level. > > For the particular example of ADAQ4216, it can have PGA control pins connected > to GPIOs. > > +-------------+ +-------------+ > | ADC | | HOST | > | | | | > | SPI lines |<=======>| SPI lines | > | | | | > | A0 |<--------| GPIO_A | > | A1 |<--------| GPIO_B | > +-------------+ +-------------+ > > But the pins might instead be hard-wired, like > > +-------------+ +-------------+ > | ADC | | HOST | > | | | | > | SPI lines |<=======>| SPI lines | > | | +-------------+ > | A0 |<-----+ > | A1 |<-----+ > +-------------+ | > VIO > > or > > +-------------+ +-------------+ > | ADC | | HOST | > | | | | > | SPI lines |<=======>| SPI lines | > | | +-------------+ > | A0 |<--------- VIO > | A1 |<-----+ > +-------------+ | > GND > > Or even, possibly, a mix of GPIO and hard-wired. > > +-------------+ +-------------+ > | ADC | | HOST | > | | | | > | SPI lines |<=======>| SPI lines | > | | | | > | A0 |<--------| GPIO_A | > | | +-------------+ > | A1 |<-----+ > +-------------+ | > GND > > We have bindings (like adi,ad7191.yaml [1]) describing the hard-wired setups > with function specific properties. E.g. > adi,pga-value: > $ref: /schemas/types.yaml#/definitions/uint32 > description: | > Should be present if PGA pins are pin-strapped. Possible values: > Gain 1 (PGA1=0, PGA2=0) > Gain 8 (PGA1=0, PGA2=1) > Gain 64 (PGA1=1, PGA2=0) > Gain 128 (PGA1=1, PGA2=1) > If defined, pga-gpios must be absent. > enum: [1, 8, 64, 128] > > This approach works fine, but it requires documenting device-specific values > (e.g. gain 1, gain 8, ..., gain X) for each new series of ADCs because each > each series has different hardware properties. > > Sometimes peripherals have pins with different functions that are also either > hard-wired or connected to GPIOs (like adi,ad7606.yaml [2] and adi,ad7625.yaml [3]). > Software wants to know about the state of those pins. When they are connected > to GPIOs, we can just read the GPIO value. But when the pins are hard-wired, > we have to set additional dt properties (e.g. adi,pga-value) and then software > figures out the state of the pins from the value read from dt. > What we wonder is whether it would be possible to have both the GPIO and > hard-wired cases described by gpio properties. > > [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml#n77 > [2]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml#n127 > [3]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7625.yaml#n70 > > For example, instead of having > > /* All GPIOs case */ > pga-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>; > > and > > /* All hard-wired (pin-strapped) case */ > adi,pga-value = <1>; > > maybe we could have something like > > /* All gpios */ > pga-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, > <&gpio0 1 GPIO_ACTIVE_HIGH>; > /* or all hard-wired */ > pga-gpios = <&fixed_gpio GPIO_FIXED_LOW>, > <&fixed_gpio GPIO_FIXED_LOW>; > > as suggested by David [4]. > > Though, I'm also a bit worried about such way of describing the hard-wired > connections being potentially confusing as those "fixed-gpios" would not > necessarily mean any actual GPIO. > > [4]: https://lore.kernel.org/linux-iio/CAMknhBHzXLjkbKAjkgRwEps=0YrOgUcdvRpuPRrcPkwfwWo88w@mail.gmail.com/ > > > With best regards, > Marcelo
On Wed, Oct 08, 2025 at 10:51:37AM -0300, Marcelo Schmitt wrote: > Change log v3 -> v4 > - Now only documenting GPIO setup to control ADAQ PGA pins. > + else: > + properties: > + adi,pga-value: false I assume this is an oversight?
On 10/08, Conor Dooley wrote: > On Wed, Oct 08, 2025 at 10:51:37AM -0300, Marcelo Schmitt wrote: > > > Change log v3 -> v4 > > - Now only documenting GPIO setup to control ADAQ PGA pins. > > > + else: > > + properties: > > + adi,pga-value: false > > I assume this is an oversight? Oops. Sure, should have dropped that. If the device is not an ADAQ (no PGA circuitry present), then we should not have properties associated to that. + else: + properties: + pga-gpios: false + Thanks, Marcelo
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