Existing rv64 hardware conforms to the rva20 profile.
Ziccrse is an additional extension required by the rva20 profile, so
th1520 has this extension.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 59d1927764a6..7f07688aa964 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -24,8 +24,10 @@ c910_0: cpu@0 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <0>;
i-cache-block-size = <64>;
@@ -49,8 +51,10 @@ c910_1: cpu@1 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <1>;
i-cache-block-size = <64>;
@@ -74,8 +78,10 @@ c910_2: cpu@2 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <2>;
i-cache-block-size = <64>;
@@ -99,8 +105,10 @@ c910_3: cpu@3 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <3>;
i-cache-block-size = <64>;
--
2.47.3