Could use docs: instead of Documentation: in the subject to
make it a bit shorter. Seems common enough.
On 9/18/25 12:38 PM, Marcelo Schmitt wrote:
> Document double PWM setup SPI offload wiring schema.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
> Change log v1 -> v2
> - Swapped PWM numbering.
> - Expanded double PWM description and capture zone description.
>
> Documentation/iio/ad4030.rst | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst
> index b57424b650a8..9501d3fee9bb 100644
> --- a/Documentation/iio/ad4030.rst
> +++ b/Documentation/iio/ad4030.rst
> @@ -92,6 +92,41 @@ Interleaved mode
> In this mode, both channels conversion results are bit interleaved one SDO line.
> As such the wiring is the same as `One lane mode`_.
>
> +SPI offload wiring
> +^^^^^^^^^^^^^^^^^^
> +
> +.. code-block::
> +
> + +-------------+ +-------------+
> + | CNV |<-----+--| GPIO |
> + | | +--| PWM0 |
> + | | | |
> + | | +--| PWM1 |
> + | | | +-------------+
> + | | +->| TRIGGER |
> + | CS |<--------| CS |
> + | | | |
> + | ADC | | SPI |
> + | | | |
> + | SDI |<--------| SDO |
> + | SDO |-------->| SDI |
> + | SCLK |<--------| SCLK |
> + +-------------+ +-------------+
> +
> +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required.
> +The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin.
> +The SPI offload will have a ``trigger-sources`` property to indicate the SPI
> +offload (PWM) trigger source. For AD4030 and similar ADCs, there are two
> +possible data transfer zones for sample N. One of them (zone 1) starts after the
> +data conversion for sample N is complete while the other one (zone 2) starts 9.8
> +nanoseconds after the rising edge of CNV for sample N + 1.
> +
> +The configuration depicted in the above ASCII art is intended to perform data
Could say "diagram" instead of "ASCII art" if you want to be more formal.
> +transfer in zone 2. To achieve high sample rates while meeting ADC timing
> +requirements, an offset is added between the rising edges of PWM0 and PWM1 to
> +delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This
> +requires a specialized PWM controller that can provide such an offset.
> +
Could add a link to the HDL project as an example of such hardware.
> SPI Clock mode
> --------------
>
Good enough as it is.
Reviewed-by: David Lechner <dlechner@baylibre.com>