From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add SPI bus width properties to correctly describe the hardware on the
following devices:
- Stratix10
- Agilex
- Agilex5
- N5X

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
changes in v2:
	- rewrite the commit message body to align with 80 characters.
	- add additional reviewer
---
Fong, Yan Kei (4):
  arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
 4 files changed, 8 insertions(+)

-- 
2.25.1

On 9/10/25 21:21, Fong, Yan Kei wrote:
> Add SPI bus width properties to correctly describe the hardware on the
> following devices:
> - Stratix10
> - Agilex
> - Agilex5
> - N5X
> 
> Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
> Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> changes in v3:
> 	- remove the unalign email shown in the commit message body
> changes in v2:
> 	- rewrite the commit message body to align with 80 characters.
> 	- add additional reviewer
>

You have a series of v2 and v3 patches in the same thread. Which ones 
should I look at?