On 8/29/25 7:41 PM, Marcelo Schmitt wrote:
> Document double PWM setup SPI offload wiring schema.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
> Documentation/iio/ad4030.rst | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst
> index b57424b650a8..dc3ac253ef66 100644
> --- a/Documentation/iio/ad4030.rst
> +++ b/Documentation/iio/ad4030.rst
> @@ -92,6 +92,35 @@ Interleaved mode
> In this mode, both channels conversion results are bit interleaved one SDO line.
> As such the wiring is the same as `One lane mode`_.
>
> +SPI offload wiring
> +^^^^^^^^^^^^^^^^^^
> +
> +.. code-block::
> +
> + +-------------+ +-------------+
> + | CNV |<-----+--| GPIO |
> + | | +--| PWM1 |
Would be more logical to swap the PWM numbers since CNV
is triggered first.
> + | | | |
> + | | +--| PWM0 |
> + | | | +-------------+
> + | | +->| TRIGGER |
> + | CS |<--------| CS |
> + | | | |
> + | ADC | | SPI |
> + | | | |
> + | SDI |<--------| SDO |
> + | SDO |-------->| SDI |
> + | SCLK |<--------| SCLK |
> + +-------------+ +-------------+
> +
> +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required.
> +The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin.
> +The SPI offload will have a ``trigger-sources`` property to indicate the SPI
> +offload (PWM) trigger source. The IIO device driver synchronizes the PWMs to do
suggest to add something like:
with an offset between the rising edge of PWM0 and PWM1 to delay the SPI
transfer until some time after the conversion. This requires a specialized
PWM controller that can provide such an offset.
> +ADC transfer zone 2 data capture.
What is "zone 2"?
> +
> +.. seealso:: `SPI offload support`_
There is no section that this links to. Add the section or delete this.
> +
> SPI Clock mode
> --------------
>