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[PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO

Christophe Leroy posted 4 patches 1 month, 3 weeks ago
There is a newer version of this series
[PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO
Posted by Christophe Leroy 1 month, 3 weeks ago 
In the QE, a few GPIOs are IRQ capable. Similarly to
commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
GPIO"), add IRQ support to QE GPIO.

Add property 'fsl,qe-gpio-irq-mask' similar to
'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.

Here is an exemple for port B of mpc8323 which has IRQs for
GPIOs PB7, PB9, PB25 and PB27.

	qe_pio_b: gpio-controller@1418 {
		#gpio-cells = <2>;
		compatible = "fsl,mpc8323-qe-pario-bank";
		reg = <0x1418 0x18>;
		interrupts = <4 5 6 7>;
		fsl,qe-gpio-irq-mask = <0x01400050>;
		interrupt-parent = <&qepic>;
		gpio-controller;
	};

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
 drivers/soc/fsl/qe/gpio.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index b502377193192..59145652ad850 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -13,6 +13,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/gpio/legacy-of-mm-gpiochip.h>
 #include <linux/gpio/consumer.h>
 #include <linux/gpio/driver.h>
@@ -32,6 +33,8 @@ struct qe_gpio_chip {
 
 	/* saved_regs used to restore dedicated functions */
 	struct qe_pio_regs saved_regs;
+
+	int irq[32];
 };
 
 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
@@ -141,6 +144,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 	return 0;
 }
 
+static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+
+	return qe_gc->irq[gpio] ? : -ENXIO;
+}
+
 struct qe_pin {
 	/*
 	 * The qe_gpio_chip name is unfortunate, we should change that to
@@ -304,6 +314,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
 	struct qe_gpio_chip *qe_gc;
 	struct of_mm_gpio_chip *mm_gc;
 	struct gpio_chip *gc;
+	u32 mask;
 
 	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
 	if (!qe_gc) {
@@ -313,6 +324,14 @@ static int qe_gpio_probe(struct platform_device *ofdev)
 
 	spin_lock_init(&qe_gc->lock);
 
+	if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) {
+		int i, j;
+
+		for (i = 0, j = 0; i < 32; i++)
+			if (mask & (1 << (31 - i)))
+				qe_gc->irq[i] = irq_of_parse_and_map(np, j++);
+	}
+
 	mm_gc = &qe_gc->mm_gc;
 	gc = &mm_gc->gc;
 
@@ -323,6 +342,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
 	gc->get = qe_gpio_get;
 	gc->set = qe_gpio_set;
 	gc->set_multiple = qe_gpio_set_multiple;
+	gc->to_irq = qe_gpio_to_irq;
 
 	ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
 	if (!ret)
-- 
2.49.0
Re: [PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO
Posted by Krzysztof Kozlowski 1 month, 3 weeks ago 
On 12/08/2025 13:02, Christophe Leroy wrote:
>  
>  	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
>  	if (!qe_gc) {
> @@ -313,6 +324,14 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>  
>  	spin_lock_init(&qe_gc->lock);
>  
> +	if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) {

Undocumented ABI. You cannot add such stuff and testing your DTS would
point it out.


Best regards,
Krzysztof
Re: [PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO
Posted by Bartosz Golaszewski 1 month, 3 weeks ago 
On Tue, 12 Aug 2025 13:02:53 +0200, Christophe Leroy
<christophe.leroy@csgroup.eu> said:
> In the QE, a few GPIOs are IRQ capable. Similarly to
> commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
> GPIO"), add IRQ support to QE GPIO.
>
> Add property 'fsl,qe-gpio-irq-mask' similar to
> 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.
>
> Here is an exemple for port B of mpc8323 which has IRQs for
> GPIOs PB7, PB9, PB25 and PB27.
>
> 	qe_pio_b: gpio-controller@1418 {
> 		#gpio-cells = <2>;
> 		compatible = "fsl,mpc8323-qe-pario-bank";
> 		reg = <0x1418 0x18>;
> 		interrupts = <4 5 6 7>;
> 		fsl,qe-gpio-irq-mask = <0x01400050>;
> 		interrupt-parent = <&qepic>;
> 		gpio-controller;
> 	};
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
>  drivers/soc/fsl/qe/gpio.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
> index b502377193192..59145652ad850 100644
> --- a/drivers/soc/fsl/qe/gpio.c
> +++ b/drivers/soc/fsl/qe/gpio.c
> @@ -13,6 +13,7 @@
>  #include <linux/err.h>
>  #include <linux/io.h>
>  #include <linux/of.h>
> +#include <linux/of_irq.h>
>  #include <linux/gpio/legacy-of-mm-gpiochip.h>
>  #include <linux/gpio/consumer.h>
>  #include <linux/gpio/driver.h>
> @@ -32,6 +33,8 @@ struct qe_gpio_chip {
>
>  	/* saved_regs used to restore dedicated functions */
>  	struct qe_pio_regs saved_regs;
> +
> +	int irq[32];
>  };
>
>  static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
> @@ -141,6 +144,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
>  	return 0;
>  }
>
> +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio)
> +{
> +	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
> +
> +	return qe_gc->irq[gpio] ? : -ENXIO;
> +}
> +
>  struct qe_pin {
>  	/*
>  	 * The qe_gpio_chip name is unfortunate, we should change that to
> @@ -304,6 +314,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>  	struct qe_gpio_chip *qe_gc;
>  	struct of_mm_gpio_chip *mm_gc;
>  	struct gpio_chip *gc;
> +	u32 mask;
>
>  	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
>  	if (!qe_gc) {
> @@ -313,6 +324,14 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>
>  	spin_lock_init(&qe_gc->lock);
>
> +	if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) {

AFAICT: you can drop the of.h include and just use
device_property_present() here.

> +		int i, j;
> +
> +		for (i = 0, j = 0; i < 32; i++)
> +			if (mask & (1 << (31 - i)))
> +				qe_gc->irq[i] = irq_of_parse_and_map(np, j++);
> +	}
> +
>  	mm_gc = &qe_gc->mm_gc;
>  	gc = &mm_gc->gc;
>
> @@ -323,6 +342,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>  	gc->get = qe_gpio_get;
>  	gc->set = qe_gpio_set;
>  	gc->set_multiple = qe_gpio_set_multiple;
> +	gc->to_irq = qe_gpio_to_irq;
>
>  	ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
>  	if (!ret)
> --
> 2.49.0
>
>

Bart
Re: [PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO
Posted by Christophe Leroy 1 month, 2 weeks ago 

Le 12/08/2025 à 16:21, Bartosz Golaszewski a écrit :
> On Tue, 12 Aug 2025 13:02:53 +0200, Christophe Leroy
> <christophe.leroy@csgroup.eu> said:
>> In the QE, a few GPIOs are IRQ capable. Similarly to
>> commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
>> GPIO"), add IRQ support to QE GPIO.
>>
>> Add property 'fsl,qe-gpio-irq-mask' similar to
>> 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.
>>
>> Here is an exemple for port B of mpc8323 which has IRQs for
>> GPIOs PB7, PB9, PB25 and PB27.
>>
>> 	qe_pio_b: gpio-controller@1418 {
>> 		#gpio-cells = <2>;
>> 		compatible = "fsl,mpc8323-qe-pario-bank";
>> 		reg = <0x1418 0x18>;
>> 		interrupts = <4 5 6 7>;
>> 		fsl,qe-gpio-irq-mask = <0x01400050>;
>> 		interrupt-parent = <&qepic>;
>> 		gpio-controller;
>> 	};
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>> ---
>>   drivers/soc/fsl/qe/gpio.c | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
>> index b502377193192..59145652ad850 100644
>> --- a/drivers/soc/fsl/qe/gpio.c
>> +++ b/drivers/soc/fsl/qe/gpio.c
>> @@ -13,6 +13,7 @@
>>   #include <linux/err.h>
>>   #include <linux/io.h>
>>   #include <linux/of.h>
>> +#include <linux/of_irq.h>
>>   #include <linux/gpio/legacy-of-mm-gpiochip.h>
>>   #include <linux/gpio/consumer.h>
>>   #include <linux/gpio/driver.h>
>> @@ -32,6 +33,8 @@ struct qe_gpio_chip {
>>
>>   	/* saved_regs used to restore dedicated functions */
>>   	struct qe_pio_regs saved_regs;
>> +
>> +	int irq[32];
>>   };
>>
>>   static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
>> @@ -141,6 +144,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
>>   	return 0;
>>   }
>>
>> +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio)
>> +{
>> +	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
>> +
>> +	return qe_gc->irq[gpio] ? : -ENXIO;
>> +}
>> +
>>   struct qe_pin {
>>   	/*
>>   	 * The qe_gpio_chip name is unfortunate, we should change that to
>> @@ -304,6 +314,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>>   	struct qe_gpio_chip *qe_gc;
>>   	struct of_mm_gpio_chip *mm_gc;
>>   	struct gpio_chip *gc;
>> +	u32 mask;
>>
>>   	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
>>   	if (!qe_gc) {
>> @@ -313,6 +324,14 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>>
>>   	spin_lock_init(&qe_gc->lock);
>>
>> +	if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) {
> 
> AFAICT: you can drop the of.h include and just use
> device_property_present() here.

This line reads the value of the mask, I can't see how it can be 
replaced by device_property_present().

> 
>> +		int i, j;
>> +
>> +		for (i = 0, j = 0; i < 32; i++)
>> +			if (mask & (1 << (31 - i)))
>> +				qe_gc->irq[i] = irq_of_parse_and_map(np, j++);
>> +	}
>> +
>>   	mm_gc = &qe_gc->mm_gc;
>>   	gc = &mm_gc->gc;
>>
>> @@ -323,6 +342,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
>>   	gc->get = qe_gpio_get;
>>   	gc->set = qe_gpio_set;
>>   	gc->set_multiple = qe_gpio_set_multiple;
>> +	gc->to_irq = qe_gpio_to_irq;
>>
>>   	ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
>>   	if (!ret)
>> --
>> 2.49.0
>>
>>
> 
> Bart

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