The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for it for that those IRQs can then
be linked to the related GPIOs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
.../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
new file mode 100644
index 0000000000000..7c98706d03dd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+title: Freescale QUICC Engine I/O Ports Interrupt Controller
+
+maintainers:
+ - name: Christophe Leroy
+ email: christophe.leroy@csgroup.eu
+
+description: |
+ Interrupt controller for the QUICC Engine I/O ports found on some
+ Freescale/NXP PowerQUICC and QorIQ SoCs.
+
+properties:
+ compatible:
+ enum:
+ - fsl,mpc8323-qe-ports-ic
+ - fsl,mpc8360-qe-ports-ic
+ - fsl,mpc8568-qe-ports-ic
+
+ reg:
+ description: Base address and size of the QE I/O Ports Interrupt Controller registers.
+ minItems: 1
+ maxItems: 1
+
+ interrupt-controller:
+ type: boolean
+ description: Indicates this node is an interrupt controller.
+
+ '#address-cells':
+ const: 0
+ description: Must be 0.
+
+ '#interrupt-cells':
+ const: 1
+ description: Number of cells to encode an interrupt specifier.
+
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ description: Interrupt line to which the QE I/O Ports controller is connected.
+
+ interrupt-parent:
+ description: Phandle to the parent interrupt controller.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupts
+ - interrupt-parent
+
+examples:
+ - |
+ interrupt-controller@c00 {
+ interrupt-controller;
+ compatible = "fsl,mpc8323-qe-ports-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0xc00 0x18>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
--
2.49.0On 12/08/2025 13:02, Christophe Leroy wrote: > The QUICC Engine provides interrupts for a few I/O ports. This is > handled via a separate interrupt ID and managed via a triplet of > dedicated registers hosted by the SoC. > > Implement an interrupt driver for it for that those IRQs can then > be linked to the related GPIOs. > > Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> > --- > .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml > new file mode 100644 > index 0000000000000..7c98706d03dd1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > + > +title: Freescale QUICC Engine I/O Ports Interrupt Controller > + > +maintainers: > + - name: Christophe Leroy > + email: christophe.leroy@csgroup.eu Oh no... > + > +description: | > + Interrupt controller for the QUICC Engine I/O ports found on some > + Freescale/NXP PowerQUICC and QorIQ SoCs. > + > +properties: > + compatible: > + enum: > + - fsl,mpc8323-qe-ports-ic > + - fsl,mpc8360-qe-ports-ic > + - fsl,mpc8568-qe-ports-ic > + > + reg: > + description: Base address and size of the QE I/O Ports Interrupt Controller registers. > + minItems: 1 > + maxItems: 1 This was never tested but more important this and everything further looks like generated by AI. Please don't do that or at least mark it clearly, so I will prioritize accordingly (hint: AI generates poor code and burden to decipher AI slop should not be on open source reviewers but on users of AI, but as one of maintainers probably you already know that, so sorry for lecturing). Best regards, Krzysztof
Le 12/08/2025 à 17:23, Krzysztof Kozlowski a écrit : > On 12/08/2025 13:02, Christophe Leroy wrote: >> The QUICC Engine provides interrupts for a few I/O ports. This is >> handled via a separate interrupt ID and managed via a triplet of >> dedicated registers hosted by the SoC. >> >> Implement an interrupt driver for it for that those IRQs can then >> be linked to the related GPIOs. >> >> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> >> --- >> .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml >> >> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml >> new file mode 100644 >> index 0000000000000..7c98706d03dd1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml >> @@ -0,0 +1,63 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> + >> +title: Freescale QUICC Engine I/O Ports Interrupt Controller >> + >> +maintainers: >> + - name: Christophe Leroy >> + email: christophe.leroy@csgroup.eu > > Oh no... > >> + >> +description: | >> + Interrupt controller for the QUICC Engine I/O ports found on some >> + Freescale/NXP PowerQUICC and QorIQ SoCs. >> + >> +properties: >> + compatible: >> + enum: >> + - fsl,mpc8323-qe-ports-ic >> + - fsl,mpc8360-qe-ports-ic >> + - fsl,mpc8568-qe-ports-ic >> + >> + reg: >> + description: Base address and size of the QE I/O Ports Interrupt Controller registers. >> + minItems: 1 >> + maxItems: 1 > > This was never tested but more important this and everything further > looks like generated by AI. Please don't do that or at least mark it > clearly, so I will prioritize accordingly (hint: AI generates poor code > and burden to decipher AI slop should not be on open source reviewers > but on users of AI, but as one of maintainers probably you already know > that, so sorry for lecturing). Yes sorry, overconfidence into AI. Until now I knew almost nothing about YAML and the generated file had a good look. I didn't know there was a special procedure to test bindings, I thought checkpatch was doing all necessary checks. Fixed in v2.
On Tue, Aug 12, 2025 at 10:23 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 12/08/2025 13:02, Christophe Leroy wrote: > > The QUICC Engine provides interrupts for a few I/O ports. This is > > handled via a separate interrupt ID and managed via a triplet of > > dedicated registers hosted by the SoC. > > > > Implement an interrupt driver for it for that those IRQs can then > > be linked to the related GPIOs. > > > > Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> > > --- > > .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++ > > 1 file changed, 63 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml > > > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml > > new file mode 100644 > > index 0000000000000..7c98706d03dd1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml > > @@ -0,0 +1,63 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > + > > +title: Freescale QUICC Engine I/O Ports Interrupt Controller > > + > > +maintainers: > > + - name: Christophe Leroy > > + email: christophe.leroy@csgroup.eu > > Oh no... > > > + > > +description: | > > + Interrupt controller for the QUICC Engine I/O ports found on some > > + Freescale/NXP PowerQUICC and QorIQ SoCs. > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,mpc8323-qe-ports-ic > > + - fsl,mpc8360-qe-ports-ic > > + - fsl,mpc8568-qe-ports-ic > > + > > + reg: > > + description: Base address and size of the QE I/O Ports Interrupt Controller registers. > > + minItems: 1 > > + maxItems: 1 > > This was never tested but more important this and everything further > looks like generated by AI. Please don't do that or at least mark it > clearly, so I will prioritize accordingly (hint: AI generates poor code > and burden to decipher AI slop should not be on open source reviewers > but on users of AI, but as one of maintainers probably you already know > that, so sorry for lecturing). If anyone needs some AI (chatgpt) converted bindings, my "dt-convert" branch has ~800 of them. Feeding the warnings back to AI to fix was somewhat effective. The result is not the worst I've seen submitted. It saves some of the boilerplate, but can't fix things that are just wrong or unclear in .txt bindings. Despite my 'prompt engineering' attempts, it still tends to get the same things wrong over and over. Rob
Le 12/08/2025 à 19:16, Rob Herring a écrit : > On Tue, Aug 12, 2025 at 10:23 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: >> >> On 12/08/2025 13:02, Christophe Leroy wrote: >>> The QUICC Engine provides interrupts for a few I/O ports. This is >>> handled via a separate interrupt ID and managed via a triplet of >>> dedicated registers hosted by the SoC. >>> >>> Implement an interrupt driver for it for that those IRQs can then >>> be linked to the related GPIOs. >>> >>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> >>> --- >>> .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++ >>> 1 file changed, 63 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml >>> new file mode 100644 >>> index 0000000000000..7c98706d03dd1 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml >>> @@ -0,0 +1,63 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> + >>> +title: Freescale QUICC Engine I/O Ports Interrupt Controller >>> + >>> +maintainers: >>> + - name: Christophe Leroy >>> + email: christophe.leroy@csgroup.eu >> >> Oh no... >> >>> + >>> +description: | >>> + Interrupt controller for the QUICC Engine I/O ports found on some >>> + Freescale/NXP PowerQUICC and QorIQ SoCs. >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - fsl,mpc8323-qe-ports-ic >>> + - fsl,mpc8360-qe-ports-ic >>> + - fsl,mpc8568-qe-ports-ic >>> + >>> + reg: >>> + description: Base address and size of the QE I/O Ports Interrupt Controller registers. >>> + minItems: 1 >>> + maxItems: 1 >> >> This was never tested but more important this and everything further >> looks like generated by AI. Please don't do that or at least mark it >> clearly, so I will prioritize accordingly (hint: AI generates poor code >> and burden to decipher AI slop should not be on open source reviewers >> but on users of AI, but as one of maintainers probably you already know >> that, so sorry for lecturing). > > If anyone needs some AI (chatgpt) converted bindings, my "dt-convert" > branch has ~800 of them. Feeding the warnings back to AI to fix was > somewhat effective. The result is not the worst I've seen submitted. > It saves some of the boilerplate, but can't fix things that are just > wrong or unclear in .txt bindings. Despite my 'prompt engineering' > attempts, it still tends to get the same things wrong over and over. By the way, the new binding was not generated from text binding. I fed the AI with the driver C source file. Christophe
On Tue, 12 Aug 2025 13:02:54 +0200, Christophe Leroy wrote:
> The QUICC Engine provides interrupts for a few I/O ports. This is
> handled via a separate interrupt ID and managed via a triplet of
> dedicated registers hosted by the SoC.
>
> Implement an interrupt driver for it for that those IRQs can then
> be linked to the related GPIOs.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml:3:1: [error] missing document start "---" (document-start)
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml: ignoring, error parsing file
Traceback (most recent call last):
File "/usr/local/bin/dt-doc-validate", line 8, in <module>
sys.exit(main())
^^^^^^
File "/usr/local/lib/python3.11/dist-packages/dtschema/doc_validate.py", line 66, in main
ret |= check_doc(f)
^^^^^^^^^^^^
File "/usr/local/lib/python3.11/dist-packages/dtschema/doc_validate.py", line 22, in check_doc
dtsch = dtschema.DTSchema(filename, line_numbers=line_number)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.11/dist-packages/dtschema/schema.py", line 83, in __init__
id = schema['$id'].rstrip('#')
~~~~~~^^^^^^^
KeyError: '$id'
Error: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.example.dts:34.3-35.1 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.dtbs:132: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1527: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/0b56ef403a7c8d0f8305e847d68959a1037d365e.1754996033.git.christophe.leroy@csgroup.eu
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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