From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the n5x device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 7952c7f47cc2..0034a4897220 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -93,6 +93,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1

On 6/24/25 01:52, yankei.fong@altera.com wrote:
> From: "Fong, Yan Kei" <yan.kei.fong@altera.com>
> 
> Add spi-tx-bus-width and spi-rx-bus-width properties with
> value 4 to the n5x device tree.
> This update configures the SPI controller to use a 4-bit
> bus width for both transmission and reception,
> potentially improving SPI throughput and
> matching the hardware capabilities more closely.

Please use 80 columns for your commit message! Like this:

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
n5x device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially 
improving SPI throughput and matching the hardware capabilities more 
closely.

Doesn't the above make it much easier to read? Please do this fall your 
patches from now on!

Dinh