[v1] Add 4-bit SPI bus width on target devices

[PATCH 0/4] Add 4-bit SPI bus width on target devices

Posted by yankei.fong@altera.com 3 months, 2 weeks ago

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add SPI bus width properties to correctly describe the hardware on the following devices:
 - Stratix10
 - Agilex
 - Agilex5
 - N5X

Fong, Yan Kei (4):
  arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
 4 files changed, 8 insertions(+)

-- 
2.25.1

Re: [PATCH 0/4] Add 4-bit SPI bus width on target devices

Posted by Dinh Nguyen 3 months, 2 weeks ago

On 6/24/25 01:52, yankei.fong@altera.com wrote:
> From: "Fong, Yan Kei" <yan.kei.fong@altera.com>
> 
> Add SPI bus width properties to correctly describe the hardware on the following devices:
>   - Stratix10
>   - Agilex
>   - Agilex5
>   - N5X
> 
> Fong, Yan Kei (4):
>    arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
>    arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
>    arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
>    arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
> 
>   arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
>   4 files changed, 8 insertions(+)
> 

This is for the QSPI driver right? I don't even see the driver using 
this property. So how would this help?

[PATCH 0/4] Add 4-bit SPI bus width on target devices

Posted by yankei.fong@altera.com 3 months, 1 week ago

From: Fong, Yan Kei <yan.kei.fong@altera.com>

The changes required for the QSPI subsystem. With this implementation, the
read performance will be greater compare to single bus width when trying
to read the QSPI flash chips. Below is the test results:

$cat /sys/kernel/debug/spi-nor/spi0.0/params
...
...
opcodes
read 0x6c  -> from micron QSPI spec, 6c indicates quad output fast read
...
...
protocols
read 1S-1S-4S