Section 17.6.10 of the RK3399 TRM "PCIe PIPE PHY registers Description"
defines asynchronous strobe TEST_WRITE which should be enabled then
disabled and seems to have been copy-pasted as of current. Adjust it.
While at it, adjust read mask which should be the same as write mask.

Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
---
 drivers/phy/rockchip/phy-rockchip-pcie.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
index 48bcc7d2b33b..35d2523ee776 100644
--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -30,9 +30,9 @@
 #define PHY_CFG_ADDR_SHIFT    1
 #define PHY_CFG_DATA_MASK     0xf
 #define PHY_CFG_ADDR_MASK     0x3f
-#define PHY_CFG_RD_MASK       0x3ff
+#define PHY_CFG_RD_MASK       0x3f
 #define PHY_CFG_WR_ENABLE     1
-#define PHY_CFG_WR_DISABLE    1
+#define PHY_CFG_WR_DISABLE    0
 #define PHY_CFG_WR_SHIFT      0
 #define PHY_CFG_WR_MASK       1
 #define PHY_CFG_PLL_LOCK      0x10
-- 
2.49.0

On 2025-06-13 6:04 pm, Geraldo Nascimento wrote:
> Section 17.6.10 of the RK3399 TRM "PCIe PIPE PHY registers Description"
> defines asynchronous strobe TEST_WRITE which should be enabled then
> disabled and seems to have been copy-pasted as of current. Adjust it.

FWIW that's a bit hard to make sense of, given that it bears no relation 
whatsoever to the naming used in the code :/

(Not least because the mapping of register fields to phy signals here is 
really a property of GRF_SOC_CON8 rather than the phy itself)

> While at it, adjust read mask which should be the same as write mask.

Which write mask? Certainly not PHY_CFG_WR_MASK... However as this 
definition is unused since 64cdc0360811 ("phy: rockchip-pcie: remove 
unused phy_rd_cfg function"), I don't see much point in touching it 
other than to remove it entirely. If it is the case that only the 
address field is significant for whatever a "read" operation actually 
means, well then that's just another job for ADDR_MASK (which I guess is 
what the open-coded business with PHY_CFG_PLL_LOCK is actually doing...)

Thanks,
Robin.

> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> ---
>   drivers/phy/rockchip/phy-rockchip-pcie.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index 48bcc7d2b33b..35d2523ee776 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -30,9 +30,9 @@
>   #define PHY_CFG_ADDR_SHIFT    1
>   #define PHY_CFG_DATA_MASK     0xf
>   #define PHY_CFG_ADDR_MASK     0x3f
> -#define PHY_CFG_RD_MASK       0x3ff
> +#define PHY_CFG_RD_MASK       0x3f
>   #define PHY_CFG_WR_ENABLE     1
> -#define PHY_CFG_WR_DISABLE    1
> +#define PHY_CFG_WR_DISABLE    0
>   #define PHY_CFG_WR_SHIFT      0
>   #define PHY_CFG_WR_MASK       1
>   #define PHY_CFG_PLL_LOCK      0x10

On Fri, Jun 20, 2025 at 03:19:06PM +0100, Robin Murphy wrote:
> Which write mask? Certainly not PHY_CFG_WR_MASK... However as this 
> definition is unused since 64cdc0360811 ("phy: rockchip-pcie: remove 
> unused phy_rd_cfg function"), I don't see much point in touching it 
> other than to remove it entirely. If it is the case that only the 
> address field is significant for whatever a "read" operation actually 
> means, well then that's just another job for ADDR_MASK (which I guess is 
> what the open-coded business with PHY_CFG_PLL_LOCK is actually doing...)

Just for the sake of posterity, Robin is right here, PHY_CFG_WR_MASK is
just hardcoded to 1, and PHY_CFG_RD_MASK should have been the same
as PHY_CFG_ADDR_MASK as Robin correctly pointed out.

Moot point since I already agreed with Bjorn and Robin to drop the read
define, and Robin was kind enough to track the exact commit where the
corresponding read function was removed. I re-injected that function
from BSP into mainline for my own debugging though, that's why I caught
the typo.

Thanks,
Geraldo Nascimento

> 
> Thanks,
> Robin.

On Fri, Jun 20, 2025 at 03:19:06PM +0100, Robin Murphy wrote:
> On 2025-06-13 6:04 pm, Geraldo Nascimento wrote:
> > Section 17.6.10 of the RK3399 TRM "PCIe PIPE PHY registers Description"
> > defines asynchronous strobe TEST_WRITE which should be enabled then
> > disabled and seems to have been copy-pasted as of current. Adjust it.
> 
> FWIW that's a bit hard to make sense of, given that it bears no relation 
> whatsoever to the naming used in the code :/
> 
> (Not least because the mapping of register fields to phy signals here is 
> really a property of GRF_SOC_CON8 rather than the phy itself)

Hi Robin,

will adjust for a better commit message, thank you.

> 
> > While at it, adjust read mask which should be the same as write mask.
> 
> Which write mask? Certainly not PHY_CFG_WR_MASK... However as this 
> definition is unused since 64cdc0360811 ("phy: rockchip-pcie: remove 
> unused phy_rd_cfg function"), I don't see much point in touching it 
> other than to remove it entirely. If it is the case that only the 
> address field is significant for whatever a "read" operation actually 
> means, well then that's just another job for ADDR_MASK (which I guess is 
> what the open-coded business with PHY_CFG_PLL_LOCK is actually doing...)

Oh, I already had agreed on Bjorn's suggestion to drop PHY_CFG_RD_MASK
for good from code, but I appreciate your input too.

Thanks,
Geraldo Nascimento

> 
> Thanks,
> Robin.
> 
> > Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> > ---
> >   drivers/phy/rockchip/phy-rockchip-pcie.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> > index 48bcc7d2b33b..35d2523ee776 100644
> > --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> > +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> > @@ -30,9 +30,9 @@
> >   #define PHY_CFG_ADDR_SHIFT    1
> >   #define PHY_CFG_DATA_MASK     0xf
> >   #define PHY_CFG_ADDR_MASK     0x3f
> > -#define PHY_CFG_RD_MASK       0x3ff
> > +#define PHY_CFG_RD_MASK       0x3f
> >   #define PHY_CFG_WR_ENABLE     1
> > -#define PHY_CFG_WR_DISABLE    1
> > +#define PHY_CFG_WR_DISABLE    0
> >   #define PHY_CFG_WR_SHIFT      0
> >   #define PHY_CFG_WR_MASK       1
> >   #define PHY_CFG_PLL_LOCK      0x10
>