"io_alloc" enables direct insertion of data from I/O devices into the L3
cache.
On AMD, "io_alloc" feature is backed by L3 Smart Data Cache Injection
Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable)
or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical
processors within the cache domain.
Introduce architecture-specific handlers to enable and disable the feature.
The SDCIAE feature details are available in APM listed below [1].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
Injection Allocation Enforcement (SDCIAE)
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
v6: Added lockdep_assert_cpus_held() in _resctrl_sdciae_enable() to protect
r->ctrl_domains.
Added more comments in include/linux/resctrl.h.
v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure.
The files monitor.c/rdtgroup.c have been split between FS and ARCH directories.
Moved prototypes of resctrl_arch_io_alloc_enable() and
resctrl_arch_get_io_alloc_enabled() to include/linux/resctrl.h.
v4: Updated the commit log to address the feedback.
v3: Passed the struct rdt_resource to resctrl_arch_get_io_alloc_enabled() instead of resource id.
Renamed the _resctrl_io_alloc_enable() to _resctrl_sdciae_enable() as it is arch specific.
Changed the return to void in _resctrl_sdciae_enable() instead of int.
Added more context in commit log and fixed few typos.
v2: Renamed the functions to simplify the code.
Renamed sdciae_capable to io_alloc_capable.
Changed the name of few arch functions similar to ABMC series.
resctrl_arch_get_io_alloc_enabled()
resctrl_arch_io_alloc_enable()
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/resctrl/internal.h | 5 ++++
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++
include/linux/resctrl.h | 21 ++++++++++++++
4 files changed, 67 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3c8113..b92b04fa9888 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -1215,6 +1215,7 @@
/* - AMD: */
#define MSR_IA32_MBA_BW_BASE 0xc0000200
#define MSR_IA32_SMBA_BW_BASE 0xc0000280
+#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
#define MSR_IA32_EVT_CFG_BASE 0xc0000400
/* AMD-V MSRs */
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 5e3c41b36437..cfa519ea2875 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -37,6 +37,9 @@ struct arch_mbm_state {
u64 prev_msr;
};
+/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
+#define SDCIAE_ENABLE_BIT 1
+
/**
* struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share
* a resource for a control function
@@ -102,6 +105,7 @@ struct msr_param {
* @mon_scale: cqm counter * mon_scale = occupancy in bytes
* @mbm_width: Monitor width, to detect and correct for overflow.
* @cdp_enabled: CDP state of this resource
+ * @sdciae_enabled: SDCIAE feature is enabled
*
* Members of this structure are either private to the architecture
* e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
@@ -115,6 +119,7 @@ struct rdt_hw_resource {
unsigned int mon_scale;
unsigned int mbm_width;
bool cdp_enabled;
+ bool sdciae_enabled;
};
static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 885026468440..3bdcd53b3ce3 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -229,6 +229,46 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l)
return rdt_resources_all[l].cdp_enabled;
}
+inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r)
+{
+ return resctrl_to_arch_res(r)->sdciae_enabled;
+}
+
+static void resctrl_sdciae_set_one_amd(void *arg)
+{
+ bool *enable = arg;
+
+ if (*enable)
+ msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+ else
+ msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+}
+
+static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
+{
+ struct rdt_ctrl_domain *d;
+
+ /* Walking r->ctrl_domains, ensure it can't race with cpuhp */
+ lockdep_assert_cpus_held();
+
+ /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
+ list_for_each_entry(d, &r->ctrl_domains, hdr.list)
+ on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
+}
+
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
+{
+ struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
+
+ if (hw_res->r_resctrl.cache.io_alloc_capable &&
+ hw_res->sdciae_enabled != enable) {
+ _resctrl_sdciae_enable(r, enable);
+ hw_res->sdciae_enabled = enable;
+ }
+
+ return 0;
+}
+
void resctrl_arch_reset_all_ctrls(struct rdt_resource *r)
{
struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
index 0e8641e41100..06e8a1821702 100644
--- a/include/linux/resctrl.h
+++ b/include/linux/resctrl.h
@@ -531,6 +531,27 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *
*/
void resctrl_arch_reset_all_ctrls(struct rdt_resource *r);
+/**
+ * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.
+ * @r: The resctrl resource.
+ * @enable: Enable (true) or disable (false) io_alloc on resource @r.
+ *
+ * This can be called from any CPU.
+ *
+ * Return:
+ * 0 on success, or non-zero on error.
+ */
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable);
+
+/**
+ * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state.
+ * @r: The resctrl resource.
+ *
+ * Return:
+ * true if io_alloc is enabled or false if disabled.
+ */
+inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r);
+
extern unsigned int resctrl_rmid_realloc_threshold;
extern unsigned int resctrl_rmid_realloc_limit;
--
2.34.1Hi Babu,
On 6/11/25 2:23 PM, Babu Moger wrote:
> "io_alloc" enables direct insertion of data from I/O devices into the L3
> cache.
Above is from resctrl perspective and resctrl does not limit this to L3. Here also
I think L3 should be dropped.
>
> On AMD, "io_alloc" feature is backed by L3 Smart Data Cache Injection
> Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable)
> or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical
> processors within the cache domain.
>
> Introduce architecture-specific handlers to enable and disable the feature.
>
> The SDCIAE feature details are available in APM listed below [1].
> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
> Injection Allocation Enforcement (SDCIAE)
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
...
> ---
> arch/x86/include/asm/msr-index.h | 1 +
> arch/x86/kernel/cpu/resctrl/internal.h | 5 ++++
> arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++
> include/linux/resctrl.h | 21 ++++++++++++++
This hints the subject prefix should be "x86,fs/resctrl".
> 4 files changed, 67 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index b7dded3c8113..b92b04fa9888 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -1215,6 +1215,7 @@
> /* - AMD: */
> #define MSR_IA32_MBA_BW_BASE 0xc0000200
> #define MSR_IA32_SMBA_BW_BASE 0xc0000280
> +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
> #define MSR_IA32_EVT_CFG_BASE 0xc0000400
>
> /* AMD-V MSRs */
> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
> index 5e3c41b36437..cfa519ea2875 100644
> --- a/arch/x86/kernel/cpu/resctrl/internal.h
> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
> @@ -37,6 +37,9 @@ struct arch_mbm_state {
> u64 prev_msr;
> };
>
> +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
> +#define SDCIAE_ENABLE_BIT 1
> +
> /**
> * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share
> * a resource for a control function
> @@ -102,6 +105,7 @@ struct msr_param {
> * @mon_scale: cqm counter * mon_scale = occupancy in bytes
> * @mbm_width: Monitor width, to detect and correct for overflow.
> * @cdp_enabled: CDP state of this resource
> + * @sdciae_enabled: SDCIAE feature is enabled
nit: "SDCIAE feature (backing "io_alloc") is enabled"
> *
> * Members of this structure are either private to the architecture
> * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
> @@ -115,6 +119,7 @@ struct rdt_hw_resource {
> unsigned int mon_scale;
> unsigned int mbm_width;
> bool cdp_enabled;
> + bool sdciae_enabled;
> };
>
> static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
> index 885026468440..3bdcd53b3ce3 100644
> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
> @@ -229,6 +229,46 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l)
> return rdt_resources_all[l].cdp_enabled;
> }
>
> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r)
As indicated by lkp the inline usage needs to be fixed.
> +{
> + return resctrl_to_arch_res(r)->sdciae_enabled;
> +}
> +
> +static void resctrl_sdciae_set_one_amd(void *arg)
> +{
> + bool *enable = arg;
> +
> + if (*enable)
> + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
> + else
> + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
> +}
> +
> +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
> +{
> + struct rdt_ctrl_domain *d;
> +
> + /* Walking r->ctrl_domains, ensure it can't race with cpuhp */
> + lockdep_assert_cpus_held();
> +
> + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
> + list_for_each_entry(d, &r->ctrl_domains, hdr.list)
> + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
> +}
> +
> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
> +{
> + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
> +
> + if (hw_res->r_resctrl.cache.io_alloc_capable &&
> + hw_res->sdciae_enabled != enable) {
> + _resctrl_sdciae_enable(r, enable);
> + hw_res->sdciae_enabled = enable;
> + }
> +
> + return 0;
> +}
> +
> void resctrl_arch_reset_all_ctrls(struct rdt_resource *r)
> {
> struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
> index 0e8641e41100..06e8a1821702 100644
> --- a/include/linux/resctrl.h
> +++ b/include/linux/resctrl.h
> @@ -531,6 +531,27 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *
> */
> void resctrl_arch_reset_all_ctrls(struct rdt_resource *r);
>
> +/**
> + * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.
> + * @r: The resctrl resource.
> + * @enable: Enable (true) or disable (false) io_alloc on resource @r.
> + *
> + * This can be called from any CPU.
> + *
> + * Return:
> + * 0 on success, or non-zero on error.
Please change to "0 on success, <0 on error" to make clear it needs to be
non-zero *and* negative to be considered error by resctrl fs.
> + */
> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable);
> +
> +/**
> + * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state.
> + * @r: The resctrl resource.
> + *
> + * Return:
> + * true if io_alloc is enabled or false if disabled.
> + */
> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r);
> +
> extern unsigned int resctrl_rmid_realloc_threshold;
> extern unsigned int resctrl_rmid_realloc_limit;
>
Reinette
Hi Reinette,
On 6/17/25 22:51, Reinette Chatre wrote:
> Hi Babu,
>
> On 6/11/25 2:23 PM, Babu Moger wrote:
>> "io_alloc" enables direct insertion of data from I/O devices into the L3
>> cache.
>
> Above is from resctrl perspective and resctrl does not limit this to L3. Here also
> I think L3 should be dropped.
Sure.
>
>>
>> On AMD, "io_alloc" feature is backed by L3 Smart Data Cache Injection
>> Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable)
>> or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical
>> processors within the cache domain.
>>
>> Introduce architecture-specific handlers to enable and disable the feature.
>>
>> The SDCIAE feature details are available in APM listed below [1].
>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
>> Injection Allocation Enforcement (SDCIAE)
>>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>
> ...
>
>> ---
>> arch/x86/include/asm/msr-index.h | 1 +
>> arch/x86/kernel/cpu/resctrl/internal.h | 5 ++++
>> arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++
>> include/linux/resctrl.h | 21 ++++++++++++++
>
> This hints the subject prefix should be "x86,fs/resctrl".
Sure.
>
>> 4 files changed, 67 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index b7dded3c8113..b92b04fa9888 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -1215,6 +1215,7 @@
>> /* - AMD: */
>> #define MSR_IA32_MBA_BW_BASE 0xc0000200
>> #define MSR_IA32_SMBA_BW_BASE 0xc0000280
>> +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
>> #define MSR_IA32_EVT_CFG_BASE 0xc0000400
>>
>> /* AMD-V MSRs */
>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
>> index 5e3c41b36437..cfa519ea2875 100644
>> --- a/arch/x86/kernel/cpu/resctrl/internal.h
>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
>> @@ -37,6 +37,9 @@ struct arch_mbm_state {
>> u64 prev_msr;
>> };
>>
>> +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
>> +#define SDCIAE_ENABLE_BIT 1
>> +
>> /**
>> * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share
>> * a resource for a control function
>> @@ -102,6 +105,7 @@ struct msr_param {
>> * @mon_scale: cqm counter * mon_scale = occupancy in bytes
>> * @mbm_width: Monitor width, to detect and correct for overflow.
>> * @cdp_enabled: CDP state of this resource
>> + * @sdciae_enabled: SDCIAE feature is enabled
>
> nit: "SDCIAE feature (backing "io_alloc") is enabled"
Sure.
>
>> *
>> * Members of this structure are either private to the architecture
>> * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
>> @@ -115,6 +119,7 @@ struct rdt_hw_resource {
>> unsigned int mon_scale;
>> unsigned int mbm_width;
>> bool cdp_enabled;
>> + bool sdciae_enabled;
>> };
>>
>> static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> index 885026468440..3bdcd53b3ce3 100644
>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> @@ -229,6 +229,46 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l)
>> return rdt_resources_all[l].cdp_enabled;
>> }
>>
>> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r)
>
> As indicated by lkp the inline usage needs to be fixed.
I am assuming that you are referring to
https://www.kernel.org/doc/html/next/process/coding-style.html#the-inline-disease
I will remove inline attribute.
>
>> +{
>> + return resctrl_to_arch_res(r)->sdciae_enabled;
>> +}
>> +
>> +static void resctrl_sdciae_set_one_amd(void *arg)
>> +{
>> + bool *enable = arg;
>> +
>> + if (*enable)
>> + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
>> + else
>> + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
>> +}
>> +
>> +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
>> +{
>> + struct rdt_ctrl_domain *d;
>> +
>> + /* Walking r->ctrl_domains, ensure it can't race with cpuhp */
>> + lockdep_assert_cpus_held();
>> +
>> + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
>> + list_for_each_entry(d, &r->ctrl_domains, hdr.list)
>> + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
>> +}
>> +
>> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
>> +{
>> + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
>> +
>> + if (hw_res->r_resctrl.cache.io_alloc_capable &&
>> + hw_res->sdciae_enabled != enable) {
>> + _resctrl_sdciae_enable(r, enable);
>> + hw_res->sdciae_enabled = enable;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> void resctrl_arch_reset_all_ctrls(struct rdt_resource *r)
>> {
>> struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
>> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
>> index 0e8641e41100..06e8a1821702 100644
>> --- a/include/linux/resctrl.h
>> +++ b/include/linux/resctrl.h
>> @@ -531,6 +531,27 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *
>> */
>> void resctrl_arch_reset_all_ctrls(struct rdt_resource *r);
>>
>> +/**
>> + * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.
>> + * @r: The resctrl resource.
>> + * @enable: Enable (true) or disable (false) io_alloc on resource @r.
>> + *
>> + * This can be called from any CPU.
>> + *
>> + * Return:
>> + * 0 on success, or non-zero on error.
>
> Please change to "0 on success, <0 on error" to make clear it needs to be
> non-zero *and* negative to be considered error by resctrl fs.
Sure.
>
>> + */
>> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable);
>> +
>> +/**
>> + * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state.
>> + * @r: The resctrl resource.
>> + *
>> + * Return:
>> + * true if io_alloc is enabled or false if disabled.
>> + */
>> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r);
>> +
>> extern unsigned int resctrl_rmid_realloc_threshold;
>> extern unsigned int resctrl_rmid_realloc_limit;
>>
>
> Reinette
>
--
Thanks
Babu Moger
Hi Babu, On 6/18/25 12:27 PM, Moger, Babu wrote: > On 6/17/25 22:51, Reinette Chatre wrote: >> On 6/11/25 2:23 PM, Babu Moger wrote: >>> static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) >>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>> index 885026468440..3bdcd53b3ce3 100644 >>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>> @@ -229,6 +229,46 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l) >>> return rdt_resources_all[l].cdp_enabled; >>> } >>> >>> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) >> >> As indicated by lkp the inline usage needs to be fixed. > > I am assuming that you are referring to > https://www.kernel.org/doc/html/next/process/coding-style.html#the-inline-disease No. I am referring to the lkp test report of an issue detected by sparse. Looks like the message was not cc'd to lkml so I cannot provide link. I paste it below. You are in "To:". > > I will remove inline attribute. The goal was to fix the broken usage of inline, but you are right that it may not be needed here. Here is the original report: > Date: Fri, 13 Jun 2025 12:18:35 +0800 > From: kernel test robot <lkp@intel.com> > To: Babu Moger <babu.moger@amd.com>, corbet@lwn.net, tony.luck@intel.com, reinette.chatre@intel.com, Dave.Martin@arm.com, james.morse@arm.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com > CC: oe-kbuild-all@lists.linux.dev, x86@kernel.org, hpa@zytor.com, akpm@linux-foundation.org, paulmck@kernel.org, rostedt@goodmis.org, thuth@redhat.com, ardb@kernel.org, gregkh@linuxfoundation.org, seanjc@google.com, thomas.lendacky@amd.com, pawan.kumar.gupta@linux.intel.com, perry.yuan@amd.com, yosry.ahmed@linux.dev, kai.huang@intel.com, xiaoyao.li@intel.com, peterz@infradead.org, kan.liang@linux.intel.com, mario.limonciello@amd.com, xin3.li@intel.com, sohil.mehta@intel.com > Subject: Re: [PATCH v6 5/8] fs/resctrl: Add user interface to enable/disable io_alloc feature > Message-ID: <202506131104.d1oo8NWe-lkp@intel.com> > In-Reply-To: <b3d8e2ccd23b295f3735fc9f5420458cfc18a896.1749677012.git.babu.moger@amd.com> > > Hi Babu, > > kernel test robot noticed the following build warnings: > > [auto build test WARNING on brauner-vfs/vfs.all] > [also build test WARNING on linus/master v6.16-rc1 next-20250612] > [cannot apply to tip/x86/core aegl/next] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Babu-Moger/x86-cpufeatures-Add-support-for-L3-Smart-Data-Cache-Injection-Allocation-Enforcement/20250612-053050 > base: https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git vfs.all > patch link: https://lore.kernel.org/r/b3d8e2ccd23b295f3735fc9f5420458cfc18a896.1749677012.git.babu.moger%40amd.com > patch subject: [PATCH v6 5/8] fs/resctrl: Add user interface to enable/disable io_alloc feature > config: i386-randconfig-061-20250613 (https://download.01.org/0day-ci/archive/20250613/202506131104.d1oo8NWe-lkp@intel.com/config) > compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250613/202506131104.d1oo8NWe-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202506131104.d1oo8NWe-lkp@intel.com/ > > sparse warnings: (new ones prefixed by >>) > fs/resctrl/rdtgroup.c: note: in included file: >>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition > > vim +553 include/linux/resctrl.h > > 48e63934badb71 Babu Moger 2025-06-11 545 > 48e63934badb71 Babu Moger 2025-06-11 546 /** > 48e63934badb71 Babu Moger 2025-06-11 547 * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state. > 48e63934badb71 Babu Moger 2025-06-11 548 * @r: The resctrl resource. > 48e63934badb71 Babu Moger 2025-06-11 549 * > 48e63934badb71 Babu Moger 2025-06-11 550 * Return: > 48e63934badb71 Babu Moger 2025-06-11 551 * true if io_alloc is enabled or false if disabled. > 48e63934badb71 Babu Moger 2025-06-11 552 */ > 48e63934badb71 Babu Moger 2025-06-11 @553 inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r); > 48e63934badb71 Babu Moger 2025-06-11 554 > > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki Reinette
Hi Reinette, On 6/18/2025 3:32 PM, Reinette Chatre wrote: > Hi Babu, > > On 6/18/25 12:27 PM, Moger, Babu wrote: > >> On 6/17/25 22:51, Reinette Chatre wrote: > >>> On 6/11/25 2:23 PM, Babu Moger wrote: > >>>> static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) >>>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> index 885026468440..3bdcd53b3ce3 100644 >>>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> @@ -229,6 +229,46 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l) >>>> return rdt_resources_all[l].cdp_enabled; >>>> } >>>> >>>> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) >>> >>> As indicated by lkp the inline usage needs to be fixed. >> >> I am assuming that you are referring to >> https://www.kernel.org/doc/html/next/process/coding-style.html#the-inline-disease > > No. I am referring to the lkp test report of an issue detected by sparse. Looks like > the message was not cc'd to lkml so I cannot provide link. I paste it below. You are in > "To:". Yes. I saw that report. It's strange why it was not cc'd to lkml. Happened few times before. > >> >> I will remove inline attribute. > > The goal was to fix the broken usage of inline, but you are right that it may > not be needed here. Sure. Will remove inline. > > Here is the original report: Thanks Babu > >> Date: Fri, 13 Jun 2025 12:18:35 +0800 >> From: kernel test robot <lkp@intel.com> >> To: Babu Moger <babu.moger@amd.com>, corbet@lwn.net, tony.luck@intel.com, reinette.chatre@intel.com, Dave.Martin@arm.com, james.morse@arm.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com >> CC: oe-kbuild-all@lists.linux.dev, x86@kernel.org, hpa@zytor.com, akpm@linux-foundation.org, paulmck@kernel.org, rostedt@goodmis.org, thuth@redhat.com, ardb@kernel.org, gregkh@linuxfoundation.org, seanjc@google.com, thomas.lendacky@amd.com, pawan.kumar.gupta@linux.intel.com, perry.yuan@amd.com, yosry.ahmed@linux.dev, kai.huang@intel.com, xiaoyao.li@intel.com, peterz@infradead.org, kan.liang@linux.intel.com, mario.limonciello@amd.com, xin3.li@intel.com, sohil.mehta@intel.com >> Subject: Re: [PATCH v6 5/8] fs/resctrl: Add user interface to enable/disable io_alloc feature >> Message-ID: <202506131104.d1oo8NWe-lkp@intel.com> >> In-Reply-To: <b3d8e2ccd23b295f3735fc9f5420458cfc18a896.1749677012.git.babu.moger@amd.com> >> >> Hi Babu, >> >> kernel test robot noticed the following build warnings: >> >> [auto build test WARNING on brauner-vfs/vfs.all] >> [also build test WARNING on linus/master v6.16-rc1 next-20250612] >> [cannot apply to tip/x86/core aegl/next] >> [If your patch is applied to the wrong git tree, kindly drop us a note. >> And when submitting patch, we suggest to use '--base' as documented in >> https://git-scm.com/docs/git-format-patch#_base_tree_information] >> >> url: https://github.com/intel-lab-lkp/linux/commits/Babu-Moger/x86-cpufeatures-Add-support-for-L3-Smart-Data-Cache-Injection-Allocation-Enforcement/20250612-053050 >> base: https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git vfs.all >> patch link: https://lore.kernel.org/r/b3d8e2ccd23b295f3735fc9f5420458cfc18a896.1749677012.git.babu.moger%40amd.com >> patch subject: [PATCH v6 5/8] fs/resctrl: Add user interface to enable/disable io_alloc feature >> config: i386-randconfig-061-20250613 (https://download.01.org/0day-ci/archive/20250613/202506131104.d1oo8NWe-lkp@intel.com/config) >> compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 >> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250613/202506131104.d1oo8NWe-lkp@intel.com/reproduce) >> >> If you fix the issue in a separate patch/commit (i.e. not just a new version of >> the same patch/commit), kindly add following tags >> | Reported-by: kernel test robot <lkp@intel.com> >> | Closes: https://lore.kernel.org/oe-kbuild-all/202506131104.d1oo8NWe-lkp@intel.com/ >> >> sparse warnings: (new ones prefixed by >>) >> fs/resctrl/rdtgroup.c: note: in included file: >>>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >>>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >>>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >>>> include/linux/resctrl.h:553:46: sparse: sparse: marked inline, but without a definition >> >> vim +553 include/linux/resctrl.h >> >> 48e63934badb71 Babu Moger 2025-06-11 545 >> 48e63934badb71 Babu Moger 2025-06-11 546 /** >> 48e63934badb71 Babu Moger 2025-06-11 547 * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state. >> 48e63934badb71 Babu Moger 2025-06-11 548 * @r: The resctrl resource. >> 48e63934badb71 Babu Moger 2025-06-11 549 * >> 48e63934badb71 Babu Moger 2025-06-11 550 * Return: >> 48e63934badb71 Babu Moger 2025-06-11 551 * true if io_alloc is enabled or false if disabled. >> 48e63934badb71 Babu Moger 2025-06-11 552 */ >> 48e63934badb71 Babu Moger 2025-06-11 @553 inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r); >> 48e63934badb71 Babu Moger 2025-06-11 554 >> >> -- >> 0-DAY CI Kernel Test Service >> https://github.com/intel/lkp-tests/wiki > > Reinette >
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