From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

This patch set adds support for the address bus size limitation by
allocating buffers with in a 32 bit address range.

-Add device tree binding to enable a quirk to support a limited address
bus size.
-Update ITS node for Agilex5 with dma_32bit_quirk.
-Add implementation to configure gfp flags to allocate buffers within
32 bit addressable range when quirk is set.

Adrian Ng Ho Yin (3):
  dt-bindings: interrupt-controller: arm,gic-v3-its: Add quirk to
    support 32 bit addressable range
  arm64: dts: socfpga: agilex5: Add dma_32bit_quirk in GIC ITS node
  irqchip: gic-v3-its: add support for 32bit addressing

 .../interrupt-controller/arm,gic-v3.yaml      |  5 ++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  1 +
 drivers/irqchip/irq-gic-v3-its.c              | 23 +++++++++++++++----
 3 files changed, 25 insertions(+), 4 deletions(-)

-- 
2.49.GIT

On Fri, 16 May 2025 05:13:31 +0100,
adrianhoyin.ng@altera.com wrote:
> 
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> This patch set adds support for the address bus size limitation by
> allocating buffers with in a 32 bit address range.
> 
> -Add device tree binding to enable a quirk to support a limited address
> bus size.
> -Update ITS node for Agilex5 with dma_32bit_quirk.
> -Add implementation to configure gfp flags to allocate buffers within
> 32 bit addressable range when quirk is set.

No. Please join the pack of other totally broken integrations and
reuse the *existing* infrastructure. You'll be in good company.

	M.

-- 
Without deviation from the norm, progress is not possible.