From: Karthik Sanagavarapu <quic_kartsana@quicinc.com>

Remove the context bank compute-cb@10 because these SMMU ids are S2-only
which is not used for S1 transaction.

Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes")
Cc: stable@kernel.org
Signed-off-by: Karthik Sanagavarapu <quic_kartsana@quicinc.com>
Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 0aa27db21f3d..81b2fba94841 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4585,14 +4585,6 @@ compute-cb@9 {
 						dma-coherent;
 					};
 
-					compute-cb@10 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <10>;
-						iommus = <&apps_smmu 0x214a 0x04a0>,
-							 <&apps_smmu 0x218a 0x0400>;
-						dma-coherent;
-					};
-
 					compute-cb@11 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <11>;
-- 
2.34.1

On 2/11/2025 1:44 PM, Ling Xu wrote:
> From: Karthik Sanagavarapu <quic_kartsana@quicinc.com>
>
> Remove the context bank compute-cb@10 because these SMMU ids are S2-only
> which is not used for S1 transaction.
>
> Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes")
> Cc: stable@kernel.org
> Signed-off-by: Karthik Sanagavarapu <quic_kartsana@quicinc.com>
> Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 --------
>   1 file changed, 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 0aa27db21f3d..81b2fba94841 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -4585,14 +4585,6 @@ compute-cb@9 {
>   						dma-coherent;
>   					};
>   
> -					compute-cb@10 {
> -						compatible = "qcom,fastrpc-compute-cb";
> -						reg = <10>;
> -						iommus = <&apps_smmu 0x214a 0x04a0>,
> -							 <&apps_smmu 0x218a 0x0400>;
Commit description seems misleading as these are nested sids and not 
S2-only. You may say you don't need it for your
usecase which is a different thing altogether.
> -						dma-coherent;
> -					};
> -
>   					compute-cb@11 {
>   						compatible = "qcom,fastrpc-compute-cb";
>   						reg = <11>;

-- 
Thanks and Regards
Pratyush Brahma

在 2/11/2025 4:44 PM, Pratyush Brahma 写道:
> 
> On 2/11/2025 1:44 PM, Ling Xu wrote:
>> From: Karthik Sanagavarapu <quic_kartsana@quicinc.com>
>>
>> Remove the context bank compute-cb@10 because these SMMU ids are S2-only
>> which is not used for S1 transaction.
>>
>> Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes")
>> Cc: stable@kernel.org
>> Signed-off-by: Karthik Sanagavarapu <quic_kartsana@quicinc.com>
>> Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 --------
>>   1 file changed, 8 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 0aa27db21f3d..81b2fba94841 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -4585,14 +4585,6 @@ compute-cb@9 {
>>                           dma-coherent;
>>                       };
>>   -                    compute-cb@10 {
>> -                        compatible = "qcom,fastrpc-compute-cb";
>> -                        reg = <10>;
>> -                        iommus = <&apps_smmu 0x214a 0x04a0>,
>> -                             <&apps_smmu 0x218a 0x0400>;
> Commit description seems misleading as these are nested sids and not S2-only. You may say you don't need it for your
> usecase which is a different thing altogether.
>> -                        dma-coherent;
>> -                    };
>> -
>>                       compute-cb@11 {
>>                           compatible = "qcom,fastrpc-compute-cb";
>>                           reg = <11>;
> 

This stream ID was recently configured as S2-only for this platform.
-- 
Thx and BRs,
Ling Xu