"io_alloc" feature that enables direct insertion of data from I/O devices
into the L3 cache.
On AMD, 'io_alloc" feature is backed by L3 Smart Data Cache Injection
Allocation Enforcement (SDCIAE). SDCIAE feature can be enabled by setting
bit 1 in MSR L3_QOS_EXT_CFG. Apply the updated SDCIAE value across all
logical processors within the QOS domain when modifying its state.
Introduce architecture-specific handlers to manage the detection and
enabling/disabling of 'io_alloc" feature.
The SDCIAE feature details are available in APM listed below [1].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
Injection Allocation Enforcement (SDCIAE)
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
v3: Passed the struct rdt_resource to resctrl_arch_get_io_alloc_enabled() instead of resource id.
Renamed the _resctrl_io_alloc_enable() to _resctrl_sdciae_enable() as it is arch specific.
Changed the return to void in _resctrl_sdciae_enable() instead of int.
Added more context in commit log and fixed few typos.
v2: Renamed the functions to simplify the code.
Renamed sdciae_capable to io_alloc_capable.
Changed the name of few arch functions similar to ABMC series.
resctrl_arch_get_io_alloc_enabled()
resctrl_arch_io_alloc_enable()
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++++++
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 32 ++++++++++++++++++++++++++
include/linux/resctrl.h | 9 ++++++++
4 files changed, 52 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 9a71880eec07..fea1f3afe197 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -1197,6 +1197,7 @@
/* - AMD: */
#define MSR_IA32_MBA_BW_BASE 0xc0000200
#define MSR_IA32_SMBA_BW_BASE 0xc0000280
+#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
#define MSR_IA32_EVT_CFG_BASE 0xc0000400
/* AMD-V MSRs */
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 20c898f09b7e..61bc609e932b 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -56,6 +56,9 @@
/* Max event bits supported */
#define MAX_EVT_CONFIG_BITS GENMASK(6, 0)
+/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
+#define SDCIAE_ENABLE_BIT 1
+
/**
* cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those that
* aren't marked nohz_full
@@ -479,6 +482,7 @@ struct rdt_parse_data {
* @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth
* Monitoring Event Configuration (BMEC) is supported.
* @cdp_enabled: CDP state of this resource
+ * @sdciae_enabled: SDCIAE feature is enabled
*
* Members of this structure are either private to the architecture
* e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
@@ -493,6 +497,7 @@ struct rdt_hw_resource {
unsigned int mbm_width;
unsigned int mbm_cfg_mask;
bool cdp_enabled;
+ bool sdciae_enabled;
};
static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
@@ -539,6 +544,11 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable);
void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain *d);
+static inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r)
+{
+ return resctrl_to_arch_res(r)->sdciae_enabled;
+}
+
/*
* To return the common struct rdt_resource, which is contained in struct
* rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource.
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 6419e04d8a7b..c5a0a31c3a85 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -1798,6 +1798,38 @@ static ssize_t mbm_local_bytes_config_write(struct kernfs_open_file *of,
return ret ?: nbytes;
}
+static void resctrl_sdciae_set_one_amd(void *arg)
+{
+ bool *enable = arg;
+
+ if (*enable)
+ msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+ else
+ msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+}
+
+static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
+{
+ struct rdt_ctrl_domain *d;
+
+ /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains*/
+ list_for_each_entry(d, &r->ctrl_domains, hdr.list)
+ on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
+}
+
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
+{
+ struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
+
+ if (hw_res->r_resctrl.cache.io_alloc_capable &&
+ hw_res->sdciae_enabled != enable) {
+ _resctrl_sdciae_enable(r, enable);
+ hw_res->sdciae_enabled = enable;
+ }
+
+ return 0;
+}
+
/* rdtgroup information files for one cache resource. */
static struct rftype res_common_files[] = {
{
diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
index dbe6461f3fbc..e77c3b37bad4 100644
--- a/include/linux/resctrl.h
+++ b/include/linux/resctrl.h
@@ -343,6 +343,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d,
*/
void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d);
+/**
+ * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.
+ * @r: The resctrl resource.
+ * @enable: Enable (1) or disable (0) the feature
+ *
+ * This can be called from any CPU.
+ */
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable);
+
extern unsigned int resctrl_rmid_realloc_threshold;
extern unsigned int resctrl_rmid_realloc_limit;
--
2.34.1Hi Babu, On 1/30/25 1:20 PM, Babu Moger wrote: > "io_alloc" feature that enables direct insertion of data from I/O devices > into the L3 cache. Above is not clear to me. Should this maybe be ""io_alloc" enables direct insertion ..." > > On AMD, 'io_alloc" feature is backed by L3 Smart Data Cache Injection (mismatch quotes around io_alloc ... also below) > Allocation Enforcement (SDCIAE). SDCIAE feature can be enabled by setting "can be enabled" -> "is enabled"? > bit 1 in MSR L3_QOS_EXT_CFG. Apply the updated SDCIAE value across all > logical processors within the QOS domain when modifying its state. ... it could also just be "Change SDCIAE state by setting (to enable) or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical processors within the cache domain." > > Introduce architecture-specific handlers to manage the detection and This patch only seem to do the enable/disable with detection done in earlier patch. > enabling/disabling of 'io_alloc" feature. > > The SDCIAE feature details are available in APM listed below [1]. > [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming > Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache > Injection Allocation Enforcement (SDCIAE) > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- ... > diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h > index dbe6461f3fbc..e77c3b37bad4 100644 > --- a/include/linux/resctrl.h > +++ b/include/linux/resctrl.h > @@ -343,6 +343,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d, > */ > void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d); > > +/** > + * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature. > + * @r: The resctrl resource. > + * @enable: Enable (1) or disable (0) the feature Please be consistent in using periods at end of sentence. This could be made more specific with: "Enable (true) or disable (false) io_alloc on resource @r." > + * > + * This can be called from any CPU. > + */ > +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable); > + > extern unsigned int resctrl_rmid_realloc_threshold; > extern unsigned int resctrl_rmid_realloc_limit; > Reinette
Hi Reinette, On 3/21/25 17:53, Reinette Chatre wrote: > Hi Babu, > > On 1/30/25 1:20 PM, Babu Moger wrote: >> "io_alloc" feature that enables direct insertion of data from I/O devices >> into the L3 cache. > > Above is not clear to me. Should this maybe be ""io_alloc" enables direct insertion ..." Sure. > > >> >> On AMD, 'io_alloc" feature is backed by L3 Smart Data Cache Injection > > (mismatch quotes around io_alloc ... also below) Sure. Will correct both. > >> Allocation Enforcement (SDCIAE). SDCIAE feature can be enabled by setting > > "can be enabled" -> "is enabled"? Sure. > >> bit 1 in MSR L3_QOS_EXT_CFG. Apply the updated SDCIAE value across all >> logical processors within the QOS domain when modifying its state. > > ... it could also just be "Change SDCIAE state by setting (to enable) or > clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical processors > within the cache domain." Sure. > >> >> Introduce architecture-specific handlers to manage the detection and > > This patch only seem to do the enable/disable with detection done in > earlier patch. Sure. Will fix it. > >> enabling/disabling of 'io_alloc" feature. Yes. Mismatched quotes. >> >> The SDCIAE feature details are available in APM listed below [1]. >> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming >> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache >> Injection Allocation Enforcement (SDCIAE) >> >> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- > > ... > >> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h >> index dbe6461f3fbc..e77c3b37bad4 100644 >> --- a/include/linux/resctrl.h >> +++ b/include/linux/resctrl.h >> @@ -343,6 +343,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d, >> */ >> void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d); >> >> +/** >> + * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature. >> + * @r: The resctrl resource. >> + * @enable: Enable (1) or disable (0) the feature > > Please be consistent in using periods at end of sentence. > This could be made more specific with: > > "Enable (true) or disable (false) io_alloc on resource @r." Sure. > >> + * >> + * This can be called from any CPU. >> + */ >> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable); >> + >> extern unsigned int resctrl_rmid_realloc_threshold; >> extern unsigned int resctrl_rmid_realloc_limit; >> > > Reinette > -- Thanks Babu Moger
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