From: Chen Wang <unicorn_wang@outlook.com>
Add binding for Sophgo SG2042 PCIe host controller.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 147 ++++++++++++++++++
1 file changed, 147 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
new file mode 100644
index 000000000000..f98e71822144
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
+
+description:
+ Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pcie-host
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: reg
+ - const: cfg
+
+ vendor-id:
+ const: 0x1f1c
+
+ device-id:
+ const: 0x2042
+
+ msi:
+ type: object
+ $ref: /schemas/interrupt-controller/msi-controller.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ compatible:
+ items:
+ - const: sophgo,sg2042-pcie-msi
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: msi
+
+ msi-parent: true
+
+ sophgo,link-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SG2042 uses Cadence IP, every IP is composed of 2 cores (called link0
+ & link1 as Cadence's term). Each core corresponds to a host bridge,
+ and each host bridge has only one root port. Their configuration
+ registers are completely independent. SG2042 integrates two Cadence IPs,
+ so there can actually be up to four host bridges. "sophgo,link-id" is
+ used to identify which core/link the PCIe host bridge node corresponds to.
+
+ The Cadence IP has two modes of operation, selected by a strap pin.
+
+ In the single-link mode, the Cadence PCIe core instance associated
+ with Link0 is connected to all the lanes and the Cadence PCIe core
+ instance associated with Link1 is inactive.
+
+ In the dual-link mode, the Cadence PCIe core instance associated
+ with Link0 is connected to the lower half of the lanes and the
+ Cadence PCIe core instance associated with Link1 is connected to
+ the upper half of the lanes.
+
+ SG2042 contains 2 Cadence IPs and configures the Cores as below:
+
+ +-- Core (Link0) <---> pcie_rc0 +-----------------+
+ | | |
+ Cadence IP 1 --+ | cdns_pcie0_ctrl |
+ | | |
+ +-- Core (Link1) <---> disabled +-----------------+
+
+ +-- Core (Link0) <---> pcie_rc1 +-----------------+
+ | | |
+ Cadence IP 2 --+ | cdns_pcie1_ctrl |
+ | | |
+ +-- Core (Link1) <---> pcie_rc2 +-----------------+
+
+ pcie_rcX is PCIe node ("sophgo,sg2042-pcie-host") defined in DTS.
+
+ Sophgo defines some new register files to add support for their MSI
+ controller inside PCIe. These new register files are defined in DTS as
+ syscon node ("sophgo,sg2042-pcie-ctrl"), i.e. "cdns_pcie0_ctrl" /
+ "cdns_pcie1_ctrl". cdns_pcieX_ctrl contains some registers shared by
+ pcie_rcX, even two RC (Link)s may share different bits of the same
+ register. For example, cdns_pcie1_ctrl contains registers shared by
+ link0 & link1 for Cadence IP 2.
+
+ "sophgo,link-id" is defined to distinguish the two RC's in one Cadence IP,
+ so we can know what registers (bits) we should use.
+
+ sophgo,syscon-pcie-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the PCIe System Controller DT node. It's required to
+ access some MSI operation registers shared by PCIe RCs.
+
+allOf:
+ - $ref: cdns-pcie-host.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vendor-id
+ - device-id
+ - sophgo,link-id
+ - sophgo,syscon-pcie-ctrl
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pcie@62000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x62000000 0x00800000>,
+ <0x48000000 0x00001000>;
+ reg-names = "reg", "cfg";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+ <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+ bus-range = <0x00 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ sophgo,link-id = <0>;
+ sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
+ msi-parent = <&msi_pcie>;
+ msi_pcie: msi {
+ compatible = "sophgo,sg2042-pcie-msi";
+ msi-controller;
+ interrupt-parent = <&intc>;
+ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ };
+ };
--
2.34.1On Wed, Jan 15, 2025 at 03:06:37PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Add binding for Sophgo SG2042 PCIe host controller.
> + sophgo,link-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + SG2042 uses Cadence IP, every IP is composed of 2 cores (called link0
> + & link1 as Cadence's term). Each core corresponds to a host bridge,
> + and each host bridge has only one root port. Their configuration
> + registers are completely independent. SG2042 integrates two Cadence IPs,
> + so there can actually be up to four host bridges. "sophgo,link-id" is
> + used to identify which core/link the PCIe host bridge node corresponds to.
IIUC, the registers of Cadence IP 1 and IP 2 are completely
independent, and if you describe both of them, you would have separate
"pcie@62000000" stanzas with separate 'reg' and 'ranges' properties.
From the driver, it does not look like the registers for Link0 and
Link1 are independent, since the driver claims the
"sophgo,sg2042-pcie-host", which includes two Cores, and it tests
pcie->link_id to select the correct register address and bit mask.
"sophgo,link-id" corresponds to Cadence documentation, but I think it
is somewhat misleading in the binding because a PCIe "Link" refers to
the downstream side of a Root Port. If we use "link-id" to identify
either Core0 or Core1 of a Cadence IP, it sort of bakes in the
idea that there can never be more than one Root Port per Core.
Since each Core is the root of a separate PCI hierarchy, it seems like
maybe there should be a stanza for the Core so there's a place where
per-hierarchy things like "linux,pci-domain" properties could go,
e.g.,
pcie@62000000 { // IP 1, single-link mode
compatible = "sophgo,sg2042-pcie-host";
reg = <...>;
ranges = <...>;
core0 {
sophgo,core-id = <0>;
linux,pci-domain = <0>;
port {
num-lanes = <4>; // all lanes
};
};
};
pcie@82000000 { // IP 2, dual-link mode
compatible = "sophgo,sg2042-pcie-host";
reg = <...>;
ranges = <...>;
core0 {
sophgo,core-id = <0>;
linux,pci-domain = <1>;
port {
num-lanes = <2>; // half of lanes
};
};
core1 {
sophgo,core-id = <1>;
linux,pci-domain = <2>;
port {
num-lanes = <2>; // half of lanes
};
};
};
> + The Cadence IP has two modes of operation, selected by a strap pin.
> +
> + In the single-link mode, the Cadence PCIe core instance associated
> + with Link0 is connected to all the lanes and the Cadence PCIe core
> + instance associated with Link1 is inactive.
> +
> + In the dual-link mode, the Cadence PCIe core instance associated
> + with Link0 is connected to the lower half of the lanes and the
> + Cadence PCIe core instance associated with Link1 is connected to
> + the upper half of the lanes.
> +
> + SG2042 contains 2 Cadence IPs and configures the Cores as below:
> +
> + +-- Core (Link0) <---> pcie_rc0 +-----------------+
> + | | |
> + Cadence IP 1 --+ | cdns_pcie0_ctrl |
> + | | |
> + +-- Core (Link1) <---> disabled +-----------------+
> +
> + +-- Core (Link0) <---> pcie_rc1 +-----------------+
> + | | |
> + Cadence IP 2 --+ | cdns_pcie1_ctrl |
> + | | |
> + +-- Core (Link1) <---> pcie_rc2 +-----------------+
> +
> + pcie_rcX is PCIe node ("sophgo,sg2042-pcie-host") defined in DTS.
> +
> + Sophgo defines some new register files to add support for their MSI
> + controller inside PCIe. These new register files are defined in DTS as
> + syscon node ("sophgo,sg2042-pcie-ctrl"), i.e. "cdns_pcie0_ctrl" /
> + "cdns_pcie1_ctrl". cdns_pcieX_ctrl contains some registers shared by
> + pcie_rcX, even two RC (Link)s may share different bits of the same
> + register. For example, cdns_pcie1_ctrl contains registers shared by
> + link0 & link1 for Cadence IP 2.
> +
> + "sophgo,link-id" is defined to distinguish the two RC's in one Cadence IP,
> + so we can know what registers (bits) we should use.
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pcie@62000000 {
> + compatible = "sophgo,sg2042-pcie-host";
> + device_type = "pci";
> + reg = <0x62000000 0x00800000>,
> + <0x48000000 0x00001000>;
> + reg-names = "reg", "cfg";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
> + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
> + bus-range = <0x00 0xff>;
> + vendor-id = <0x1f1c>;
> + device-id = <0x2042>;
> + cdns,no-bar-match-nbits = <48>;
> + sophgo,link-id = <0>;
> + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
> + msi-parent = <&msi_pcie>;
> + msi_pcie: msi {
> + compatible = "sophgo,sg2042-pcie-msi";
> + msi-controller;
> + interrupt-parent = <&intc>;
> + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + };
> + };
It would be helpful for me if the example showed how both link-id 0
and link-id 1 would be used (or whatever they end up being named).
I assume both have to be somewhere in the same pcie@62000000 device to
make this work.
Bjorn
On Wed, Jan 15, 2025 at 03:06:37PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Add binding for Sophgo SG2042 PCIe host controller.
>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 147 ++++++++++++++++++
> 1 file changed, 147 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
> new file mode 100644
> index 000000000000..f98e71822144
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
> @@ -0,0 +1,147 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
> +
> +description:
> + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
> +
> +maintainers:
> + - Chen Wang <unicorn_wang@outlook.com>
> +
> +properties:
> + compatible:
> + const: sophgo,sg2042-pcie-host
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: reg
> + - const: cfg
> +
> + vendor-id:
> + const: 0x1f1c
> +
> + device-id:
> + const: 0x2042
> +
> + msi:
> + type: object
> + $ref: /schemas/interrupt-controller/msi-controller.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + compatible:
> + items:
> + - const: sophgo,sg2042-pcie-msi
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + const: msi
> +
> + msi-parent: true
> +
> + sophgo,link-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + SG2042 uses Cadence IP, every IP is composed of 2 cores (called link0
> + & link1 as Cadence's term). Each core corresponds to a host bridge,
> + and each host bridge has only one root port. Their configuration
> + registers are completely independent. SG2042 integrates two Cadence IPs,
> + so there can actually be up to four host bridges. "sophgo,link-id" is
> + used to identify which core/link the PCIe host bridge node corresponds to.
> +
> + The Cadence IP has two modes of operation, selected by a strap pin.
> +
> + In the single-link mode, the Cadence PCIe core instance associated
> + with Link0 is connected to all the lanes and the Cadence PCIe core
> + instance associated with Link1 is inactive.
> +
> + In the dual-link mode, the Cadence PCIe core instance associated
> + with Link0 is connected to the lower half of the lanes and the
> + Cadence PCIe core instance associated with Link1 is connected to
> + the upper half of the lanes.
> +
> + SG2042 contains 2 Cadence IPs and configures the Cores as below:
> +
> + +-- Core (Link0) <---> pcie_rc0 +-----------------+
> + | | |
> + Cadence IP 1 --+ | cdns_pcie0_ctrl |
> + | | |
> + +-- Core (Link1) <---> disabled +-----------------+
> +
> + +-- Core (Link0) <---> pcie_rc1 +-----------------+
> + | | |
> + Cadence IP 2 --+ | cdns_pcie1_ctrl |
> + | | |
> + +-- Core (Link1) <---> pcie_rc2 +-----------------+
> +
> + pcie_rcX is PCIe node ("sophgo,sg2042-pcie-host") defined in DTS.
> +
> + Sophgo defines some new register files to add support for their MSI
> + controller inside PCIe. These new register files are defined in DTS as
> + syscon node ("sophgo,sg2042-pcie-ctrl"), i.e. "cdns_pcie0_ctrl" /
> + "cdns_pcie1_ctrl". cdns_pcieX_ctrl contains some registers shared by
> + pcie_rcX, even two RC (Link)s may share different bits of the same
> + register. For example, cdns_pcie1_ctrl contains registers shared by
> + link0 & link1 for Cadence IP 2.
> +
> + "sophgo,link-id" is defined to distinguish the two RC's in one Cadence IP,
> + so we can know what registers (bits) we should use.
> +
> + sophgo,syscon-pcie-ctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the PCIe System Controller DT node. It's required to
> + access some MSI operation registers shared by PCIe RCs.
> +
> +allOf:
> + - $ref: cdns-pcie-host.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - vendor-id
> + - device-id
> + - sophgo,link-id
> + - sophgo,syscon-pcie-ctrl
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pcie@62000000 {
> + compatible = "sophgo,sg2042-pcie-host";
> + device_type = "pci";
> + reg = <0x62000000 0x00800000>,
> + <0x48000000 0x00001000>;
Use single space between address and size.
> + reg-names = "reg", "cfg";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
> + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
For sure you don't need to set 'relocatable' flag for both regions.
> + bus-range = <0x00 0xff>;
> + vendor-id = <0x1f1c>;
> + device-id = <0x2042>;
As Bjorn explained in v2, these properties need to be moved to PCI root port
node. Your argument of a single root port node for a host bridge doesn't add as
we have found that describing the root port properties in host bridge only
creates issues.
Btw, we are migrating the existing single RP platforms too to root port node.
> + cdns,no-bar-match-nbits = <48>;
> + sophgo,link-id = <0>;
> + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
Where is the num-lanes property?
> + msi-parent = <&msi_pcie>;
> + msi_pcie: msi {
'msi' is not a standard node name. 'interrupt-controller' is what usually used
to describe the MSI node.
Btw, is the MSI controller a separate IP inside the host bridge? If not, there
would no need to add a separate node. Most of the host bridge IPs implementing
MSI controller, do not use a separate node.
- Mani
--
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