RaspberryPi RP1 is a multi function PCI endpoint device that
exposes several subperipherals via PCI BAR.
Add a dtb overlay that will be compiled into a binary blob
and linked in the RP1 driver.
This overlay offers just minimal support to represent the
RP1 device itself, the sub-peripherals will be added by
future patches.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
---
NOTE: this patch should be taken by the same maintainer that will take
"[PATCH v3 10/12] misc: rp1: RaspberryPi RP1 misc driver", since they
are closely related in terms of compiling.
MAINTAINERS | 1 +
arch/arm64/boot/dts/broadcom/rp1.dtso | 61 +++++++++++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 arch/arm64/boot/dts/broadcom/rp1.dtso
diff --git a/MAINTAINERS b/MAINTAINERS
index 06277969a522..510a071ede78 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19383,6 +19383,7 @@ F: include/uapi/linux/media/raspberrypi/
RASPBERRY PI RP1 PCI DRIVER
M: Andrea della Porta <andrea.porta@suse.com>
S: Maintained
+F: arch/arm64/boot/dts/broadcom/rp1.dtso
F: Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml
F: Documentation/devicetree/bindings/misc/pci1de4,1.yaml
F: Documentation/devicetree/bindings/pci/pci-ep-bus.yaml
diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtso b/arch/arm64/boot/dts/broadcom/rp1.dtso
new file mode 100644
index 000000000000..8d1bbf207a30
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/rp1.dtso
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target-path="";
+ __overlay__ {
+ compatible = "pci1de4,1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ pci_ep_bus: pci-ep-bus@1 {
+ compatible = "simple-bus";
+ ranges = <0xc0 0x40000000
+ 0x01 0x00 0x00000000
+ 0x00 0x00400000>;
+ dma-ranges = <0x10 0x00000000
+ 0x43000000 0x10 0x00000000
+ 0x10 0x00000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rp1_clocks: clocks@c040018000 {
+ compatible = "raspberrypi,rp1-clocks";
+ reg = <0xc0 0x40018000 0x0 0x10038>;
+ #clock-cells = <1>;
+ clocks = <&clk_rp1_xosc>;
+ clock-names = "xosc";
+ assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>,
+ <&rp1_clocks RP1_PLL_SYS>,
+ <&rp1_clocks RP1_CLK_SYS>;
+ assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE
+ <200000000>, // RP1_PLL_SYS
+ <200000000>; // RP1_CLK_SYS
+ };
+
+ rp1_gpio: pinctrl@c0400d0000 {
+ compatible = "raspberrypi,rp1-gpio";
+ reg = <0xc0 0x400d0000 0x0 0xc000>,
+ <0xc0 0x400e0000 0x0 0xc000>,
+ <0xc0 0x400f0000 0x0 0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+ };
+};
--
2.35.3
Hi Andrea, On 10/28/24 16:07, Andrea della Porta wrote: > RaspberryPi RP1 is a multi function PCI endpoint device that > exposes several subperipherals via PCI BAR. > Add a dtb overlay that will be compiled into a binary blob > and linked in the RP1 driver. > This overlay offers just minimal support to represent the > RP1 device itself, the sub-peripherals will be added by > future patches. > > Signed-off-by: Andrea della Porta <andrea.porta@suse.com> > --- > NOTE: this patch should be taken by the same maintainer that will take > "[PATCH v3 10/12] misc: rp1: RaspberryPi RP1 misc driver", since they > are closely related in terms of compiling. > > MAINTAINERS | 1 + > arch/arm64/boot/dts/broadcom/rp1.dtso | 61 +++++++++++++++++++++++++++ > 2 files changed, 62 insertions(+) > create mode 100644 arch/arm64/boot/dts/broadcom/rp1.dtso > > diff --git a/MAINTAINERS b/MAINTAINERS > index 06277969a522..510a071ede78 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -19383,6 +19383,7 @@ F: include/uapi/linux/media/raspberrypi/ > RASPBERRY PI RP1 PCI DRIVER > M: Andrea della Porta <andrea.porta@suse.com> > S: Maintained > +F: arch/arm64/boot/dts/broadcom/rp1.dtso > F: Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml > F: Documentation/devicetree/bindings/misc/pci1de4,1.yaml > F: Documentation/devicetree/bindings/pci/pci-ep-bus.yaml > diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtso b/arch/arm64/boot/dts/broadcom/rp1.dtso > new file mode 100644 > index 000000000000..8d1bbf207a30 > --- /dev/null > +++ b/arch/arm64/boot/dts/broadcom/rp1.dtso > @@ -0,0 +1,61 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/clock/raspberrypi,rp1-clocks.h> > + > +/dts-v1/; > +/plugin/; > + > +/ { > + fragment@0 { > + target-path=""; > + __overlay__ { > + compatible = "pci1de4,1"; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + pci_ep_bus: pci-ep-bus@1 { > + compatible = "simple-bus"; > + ranges = <0xc0 0x40000000 > + 0x01 0x00 0x00000000 > + 0x00 0x00400000>; > + dma-ranges = <0x10 0x00000000 > + 0x43000000 0x10 0x00000000 > + 0x10 0x00000000>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + rp1_clocks: clocks@c040018000 { > + compatible = "raspberrypi,rp1-clocks"; > + reg = <0xc0 0x40018000 0x0 0x10038>; shouldn't this be: rp1_clocks: clocks@18000 { reg = <0x00 0x00018000 0x0 0x10038>; ... } ? And for other nodes too... ~Stan > + #clock-cells = <1>; > + clocks = <&clk_rp1_xosc>; > + clock-names = "xosc"; > + assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>, > + <&rp1_clocks RP1_PLL_SYS>, > + <&rp1_clocks RP1_CLK_SYS>; > + assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE > + <200000000>, // RP1_PLL_SYS > + <200000000>; // RP1_CLK_SYS > + }; > + > + rp1_gpio: pinctrl@c0400d0000 { > + compatible = "raspberrypi,rp1-gpio"; > + reg = <0xc0 0x400d0000 0x0 0xc000>, > + <0xc0 0x400e0000 0x0 0xc000>, > + <0xc0 0x400f0000 0x0 0xc000>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, > + <1 IRQ_TYPE_LEVEL_HIGH>, > + <2 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > + }; > +};
Hi Stan, On 15:29 Mon 04 Nov , Stanimir Varbanov wrote: > Hi Andrea, > > On 10/28/24 16:07, Andrea della Porta wrote: > > RaspberryPi RP1 is a multi function PCI endpoint device that > > exposes several subperipherals via PCI BAR. > > Add a dtb overlay that will be compiled into a binary blob > > and linked in the RP1 driver. > > This overlay offers just minimal support to represent the > > RP1 device itself, the sub-peripherals will be added by > > future patches. > > > > Signed-off-by: Andrea della Porta <andrea.porta@suse.com> > > --- > > NOTE: this patch should be taken by the same maintainer that will take > > "[PATCH v3 10/12] misc: rp1: RaspberryPi RP1 misc driver", since they > > are closely related in terms of compiling. > > > > MAINTAINERS | 1 + > > arch/arm64/boot/dts/broadcom/rp1.dtso | 61 +++++++++++++++++++++++++++ > > 2 files changed, 62 insertions(+) > > create mode 100644 arch/arm64/boot/dts/broadcom/rp1.dtso > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 06277969a522..510a071ede78 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -19383,6 +19383,7 @@ F: include/uapi/linux/media/raspberrypi/ > > RASPBERRY PI RP1 PCI DRIVER > > M: Andrea della Porta <andrea.porta@suse.com> > > S: Maintained > > +F: arch/arm64/boot/dts/broadcom/rp1.dtso > > F: Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml > > F: Documentation/devicetree/bindings/misc/pci1de4,1.yaml > > F: Documentation/devicetree/bindings/pci/pci-ep-bus.yaml > > diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtso b/arch/arm64/boot/dts/broadcom/rp1.dtso > > new file mode 100644 > > index 000000000000..8d1bbf207a30 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/broadcom/rp1.dtso > > @@ -0,0 +1,61 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/clock/raspberrypi,rp1-clocks.h> > > + > > +/dts-v1/; > > +/plugin/; > > + > > +/ { > > + fragment@0 { > > + target-path=""; > > + __overlay__ { > > + compatible = "pci1de4,1"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + > > + pci_ep_bus: pci-ep-bus@1 { > > + compatible = "simple-bus"; > > + ranges = <0xc0 0x40000000 > > + 0x01 0x00 0x00000000 > > + 0x00 0x00400000>; > > + dma-ranges = <0x10 0x00000000 > > + 0x43000000 0x10 0x00000000 > > + 0x10 0x00000000>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + rp1_clocks: clocks@c040018000 { > > + compatible = "raspberrypi,rp1-clocks"; > > + reg = <0xc0 0x40018000 0x0 0x10038>; > > shouldn't this be: > > rp1_clocks: clocks@18000 { > reg = <0x00 0x00018000 0x0 0x10038>; > ... > } > > ? > > And for other nodes too... For that to be @18000 instead of @c040018000, you should also change the "ranges" entry in pci-ep-bus node, as follows: ranges = <0x00 0x00018000 //This was: 0xc0 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>; which is of course feasible, but I prefer to use addresses that resemble (at least to some extent) the ones in RP1 docs. Many thanks, Andrea > > ~Stan > > > + #clock-cells = <1>; > > + clocks = <&clk_rp1_xosc>; > > + clock-names = "xosc"; > > + assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>, > > + <&rp1_clocks RP1_PLL_SYS>, > > + <&rp1_clocks RP1_CLK_SYS>; > > + assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE > > + <200000000>, // RP1_PLL_SYS > > + <200000000>; // RP1_CLK_SYS > > + }; > > + > > + rp1_gpio: pinctrl@c0400d0000 { > > + compatible = "raspberrypi,rp1-gpio"; > > + reg = <0xc0 0x400d0000 0x0 0xc000>, > > + <0xc0 0x400e0000 0x0 0xc000>, > > + <0xc0 0x400f0000 0x0 0xc000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, > > + <1 IRQ_TYPE_LEVEL_HIGH>, > > + <2 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + }; > > + }; > > +}; >
Hi Stan, On 15:31 Tue 05 Nov , Andrea della Porta wrote: > Hi Stan, > > On 15:29 Mon 04 Nov , Stanimir Varbanov wrote: > > Hi Andrea, > > ... > > shouldn't this be: > > > > rp1_clocks: clocks@18000 { > > reg = <0x00 0x00018000 0x0 0x10038>; > > ... > > } > > > > ? > > > > And for other nodes too... > > For that to be @18000 instead of @c040018000, you should also change > the "ranges" entry in pci-ep-bus node, as follows: > > ranges = <0x00 0x00018000 //This was: 0xc0 0x40000000 > 0x01 0x00 0x00000000 > 0x00 0x00400000>; > > which is of course feasible, but I prefer to use addresses that > resemble (at least to some extent) the ones in RP1 docs. > > Many thanks, > Andrea Sorry, this should be like this ranges = <0x00 0x00000000 //This was: 0xc0 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>; i.e. the child address in the range should be 0 and not 0x18000. Anyway you got the point: in theory we can replace that address with whatever placeholder we want and from a functional perspective, it will work, as long as you change all the relevant mappings. After some brainstorming we've decided to choose a simpler scheme that will resemble more the internal address described in the RP1 reference manual. 0xC040000000 will become 0x40000000. Many thanks, Andrea ...
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