Add the "ref-cycles" event for AMD processors based on Zen 4 and later
microarchitectures. The backing event is based on PMCx120 which counts
cycles not in halt state in P0 frequency (same as MPERF).
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
arch/x86/events/amd/core.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index afe4a809f2ed..685bfa860d67 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
};
+static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
+{
+ [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
+ [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
+ [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
+ [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
+};
+
static u64 amd_pmu_event_map(int hw_event)
{
+ if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
+ return amd_zen4_perfmon_event_map[hw_event];
+
if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
return amd_zen2_perfmon_event_map[hw_event];
--
2.34.1On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <sandipan.das@amd.com> wrote:
>
> Add the "ref-cycles" event for AMD processors based on Zen 4 and later
> microarchitectures. The backing event is based on PMCx120 which counts
> cycles not in halt state in P0 frequency (same as MPERF).
This reminds me that we lack smi cost and an smi_cycles metric for
AMD, here is an Intel one:
https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json?h=perf-tools-next#n274
The metric uses APERF but runs with freeze_on_smi set:
https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/builtin-stat.c?h=perf-tools-next#n2115
so the delta between cycles and aperf is the cycles in SMI. It would
be great if we could get something similar on AMD.
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Thanks,
Ian
> ---
> arch/x86/events/amd/core.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index afe4a809f2ed..685bfa860d67 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
> [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
> };
>
> +static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
> +{
> + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
> + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
> + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
> + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
> + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
> + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
> +};
> +
> static u64 amd_pmu_event_map(int hw_event)
> {
> + if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
> + return amd_zen4_perfmon_event_map[hw_event];
> +
> if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
> return amd_zen2_perfmon_event_map[hw_event];
>
> --
> 2.34.1
>
On 3/25/2024 8:13 PM, Ian Rogers wrote:
> On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <sandipan.das@amd.com> wrote:
>>
>> Add the "ref-cycles" event for AMD processors based on Zen 4 and later
>> microarchitectures. The backing event is based on PMCx120 which counts
>> cycles not in halt state in P0 frequency (same as MPERF).
>
> This reminds me that we lack smi cost and an smi_cycles metric for
> AMD, here is an Intel one:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json?h=perf-tools-next#n274
> The metric uses APERF but runs with freeze_on_smi set:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/builtin-stat.c?h=perf-tools-next#n2115
> so the delta between cycles and aperf is the cycles in SMI. It would
> be great if we could get something similar on AMD.
>
Thanks for the suggestion. I found PMCx02B ("ls_smi_rx" in perf JSONs) in
the AMD PPRs which counts the number of SMIs received but there's no way
to know how many cycles were spent in System Management Mode. I also could
not find an equivalent for the Freeze on SMI feature.
>> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
>
> Reviewed-by: Ian Rogers <irogers@google.com>
>
> Thanks,
> Ian
>
>> ---
>> arch/x86/events/amd/core.c | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
>> index afe4a809f2ed..685bfa860d67 100644
>> --- a/arch/x86/events/amd/core.c
>> +++ b/arch/x86/events/amd/core.c
>> @@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
>> };
>>
>> +static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> +{
>> + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
>> + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
>> + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
>> + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
>> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
>> + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
>> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
>> + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
>> +};
>> +
>> static u64 amd_pmu_event_map(int hw_event)
>> {
>> + if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
>> + return amd_zen4_perfmon_event_map[hw_event];
>> +
>> if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
>> return amd_zen2_perfmon_event_map[hw_event];
>>
>> --
>> 2.34.1
>>
On Mon, Mar 25, 2024 at 11:16 PM Sandipan Das <sandipan.das@amd.com> wrote:
>
> On 3/25/2024 8:13 PM, Ian Rogers wrote:
> > On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <sandipan.das@amd.com> wrote:
> >>
> >> Add the "ref-cycles" event for AMD processors based on Zen 4 and later
> >> microarchitectures. The backing event is based on PMCx120 which counts
> >> cycles not in halt state in P0 frequency (same as MPERF).
> >
> > This reminds me that we lack smi cost and an smi_cycles metric for
> > AMD, here is an Intel one:
> > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json?h=perf-tools-next#n274
> > The metric uses APERF but runs with freeze_on_smi set:
> > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/builtin-stat.c?h=perf-tools-next#n2115
> > so the delta between cycles and aperf is the cycles in SMI. It would
> > be great if we could get something similar on AMD.
> >
>
> Thanks for the suggestion. I found PMCx02B ("ls_smi_rx" in perf JSONs) in
> the AMD PPRs which counts the number of SMIs received but there's no way
> to know how many cycles were spent in System Management Mode. I also could
> not find an equivalent for the Freeze on SMI feature.
Thanks Sandipan, I found similar. Fwiw on Intel I'd written this in
the new (out for review) python format stuff:
https://lore.kernel.org/lkml/20240314055919.1979781-4-irogers@google.com/
Ian
> >> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> >
> > Reviewed-by: Ian Rogers <irogers@google.com>
> >
> > Thanks,
> > Ian
> >
> >> ---
> >> arch/x86/events/amd/core.c | 15 +++++++++++++++
> >> 1 file changed, 15 insertions(+)
> >>
> >> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> >> index afe4a809f2ed..685bfa860d67 100644
> >> --- a/arch/x86/events/amd/core.c
> >> +++ b/arch/x86/events/amd/core.c
> >> @@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
> >> [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
> >> };
> >>
> >> +static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
> >> +{
> >> + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
> >> + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
> >> + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
> >> + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
> >> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
> >> + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
> >> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
> >> + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
> >> +};
> >> +
> >> static u64 amd_pmu_event_map(int hw_event)
> >> {
> >> + if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
> >> + return amd_zen4_perfmon_event_map[hw_event];
> >> +
> >> if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
> >> return amd_zen2_perfmon_event_map[hw_event];
> >>
> >> --
> >> 2.34.1
> >>
>
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