From: Chen Wang <unicorn_wang@outlook.com>

Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.

Now only support basic uart drivers to boot up into a basic console.

Thanks,
Chen

---

Changes in v5:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [7].
  - dts: changed plic to support external interrupt
  - pickup improvements from Conor, details refer to [8].

Changes in v4:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [6].
  - Update bindings files for sg2042 clint as per intput from reviewers:
    - rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer
      to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
    - rename compatible strings accordingly.
  - Update dts as per input from reviewers: don't use macro for cpus's isa
    properties; use new compatible strings for mtimer/mswi of clint.
  - Use only one email-address for SoB.

Changes in v3 [v3]:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [5].
  - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
  - updated maintainers info. for sophgo devicetree
  - remove the quirk changes for uart
  - updated dts, such as:
    - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
    - update l2 cache node's name
    - remove memory and pmu nodes
  - fixed other issues as per input from reviewers.

Changes in v2 [v2]:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [4].
  - Improve format for comment of commitments as per input from last review.
  - Improve format of DTS as per input from last review.
  - Remove numa related stuff from DTS. This part is just for optimization, may
    add it later if really needed.

Changes in v1:
   The patch series is based on v6.6-rc1. Due to it is not sent in thread,
   I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
   quick reference. You can simply review or test the patches at the link [3].

[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
[7]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v5
[8]: https://lore.kernel.org/linux-riscv/20231006-empathy-unrefined-ff1168095093@spud/
[v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
[v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
[v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
[v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
[v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
[v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
[v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
[v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
[v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
[v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
[v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
[v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
[v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
[v2]:https://lore.kernel.org/linux-riscv/cover.1695189879.git.wangchen20@iscas.ac.cn/
[v3]:https://lore.kernel.org/linux-riscv/cover.1695804418.git.unicornxw@gmail.com/

---

Chen Wang (8):
  riscv: Add SOPHGO SOC family Kconfig support
  dt-bindings: vendor-prefixes: add milkv/sophgo
  dt-bindings: riscv: add sophgo sg2042 bindings
  dt-bindings: riscv: Add T-HEAD C920 compatibles
  dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
  riscv: dts: add initial Sophgo SG2042 SoC device tree
  riscv: dts: sophgo: add Milk-V Pioneer board device tree
  riscv: defconfig: enable SOPHGO SoC

Inochi Amaoto (2):
  dt-bindings: timer: Add Sophgo sg2042 CLINT timer
  dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi

 .../sifive,plic-1.0.0.yaml                    |    1 +
 .../thead,c900-aclint-mswi.yaml               |   43 +
 .../devicetree/bindings/riscv/cpus.yaml       |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
 .../timer/thead,c900-aclint-mtimer.yaml       |   43 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
 MAINTAINERS                                   |    7 +
 arch/riscv/Kconfig.socs                       |    5 +
 arch/riscv/boot/dts/Makefile                  |    1 +
 arch/riscv/boot/dts/sophgo/Makefile           |    2 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 2000 +++++++++++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  325 +++
 arch/riscv/configs/defconfig                  |    3 +-
 14 files changed, 2481 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi


base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
-- 
2.25.1

On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
> 
> Now only support basic uart drivers to boot up into a basic console.
> 
> Thanks,
> Chen
> 
> ---
> 
> Changes in v5:
>   The patch series is based on v6.6-rc1. You can simply review or test
>   the patches at the link [7].
>   - dts: changed plic to support external interrupt
>   - pickup improvements from Conor, details refer to [8].

Did you? I only see them partially picked up. I'll just replace patch 8
with the patch 8 from this series I think.

On 2023/10/7 18:17, Conor Dooley wrote:
> On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
>> in a standard mATX form factor. Add minimal device
>> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>>
>> Now only support basic uart drivers to boot up into a basic console.
>>
>> Thanks,
>> Chen
>>
>> ---
>>
>> Changes in v5:
>>    The patch series is based on v6.6-rc1. You can simply review or test
>>    the patches at the link [7].
>>    - dts: changed plic to support external interrupt
>>    - pickup improvements from Conor, details refer to [8].
> Did you? I only see them partially picked up. I'll just replace patch 8
> with the patch 8 from this series I think.

Yes, only the patch 8 of this series(v5) is updated for plic node. For 
other patches, I just cherry-picked them from previous "sophon" branch.

BTW, what I did this time may be a bit redundant. I would like to ask, 
if I encounter a similar situation in the future (that is, only one 
patch needs to be modified, and the others remain unchanged), is there a 
better way to submit the patchset?

Thanks,

Chen

On Sat, Oct 07, 2023 at 06:58:51PM +0800, Chen Wang wrote:
> 
> On 2023/10/7 18:17, Conor Dooley wrote:
> > On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
> > > From: Chen Wang <unicorn_wang@outlook.com>
> > > 
> > > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > > in a standard mATX form factor. Add minimal device
> > > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> > > 
> > > Now only support basic uart drivers to boot up into a basic console.
> > > 
> > > Thanks,
> > > Chen
> > > 
> > > ---
> > > 
> > > Changes in v5:
> > >    The patch series is based on v6.6-rc1. You can simply review or test
> > >    the patches at the link [7].
> > >    - dts: changed plic to support external interrupt
> > >    - pickup improvements from Conor, details refer to [8].
> > Did you? I only see them partially picked up. I'll just replace patch 8
> > with the patch 8 from this series I think.
> 
> Yes, only the patch 8 of this series(v5) is updated for plic node. For other
> patches, I just cherry-picked them from previous "sophon" branch.

But added my signoff? I ended up seeing my signoff on the patch where I
disagreed with the commit message, which was confusing to me.

> BTW, what I did this time may be a bit redundant. I would like to ask, if I
> encounter a similar situation in the future (that is, only one patch needs
> to be modified, and the others remain unchanged), is there a better way to
> submit the patchset?

You could have sent the plic change as a incremental change on top. So a
new patch with just that one change in it.

Thanks,
Conor.

On 2023/10/7 19:04, Conor Dooley wrote:
> On Sat, Oct 07, 2023 at 06:58:51PM +0800, Chen Wang wrote:
>> On 2023/10/7 18:17, Conor Dooley wrote:
>>> On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
>>>> From: Chen Wang <unicorn_wang@outlook.com>
>>>>
>>>> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
>>>> in a standard mATX form factor. Add minimal device
>>>> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>>>>
>>>> Now only support basic uart drivers to boot up into a basic console.
>>>>
>>>> Thanks,
>>>> Chen
>>>>
>>>> ---
>>>>
>>>> Changes in v5:
>>>>     The patch series is based on v6.6-rc1. You can simply review or test
>>>>     the patches at the link [7].
>>>>     - dts: changed plic to support external interrupt
>>>>     - pickup improvements from Conor, details refer to [8].
>>> Did you? I only see them partially picked up. I'll just replace patch 8
>>> with the patch 8 from this series I think.
>> Yes, only the patch 8 of this series(v5) is updated for plic node. For other
>> patches, I just cherry-picked them from previous "sophon" branch.
> But added my signoff? I ended up seeing my signoff on the patch where I
> disagreed with the commit message, which was confusing to me.

Oh, I used to think I can keep the exising signoff and I didn't mean to 
add it. Anyway, I agree your suggestion to create a new patch with only 
one change should be better, I will follow this in later work.

Regarding your changes on sg2042 series, I have acked in another email : 
https://lore.kernel.org/linux-riscv/MA0P287MB0332BA73D0135CC73CAEA16DFEC8A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/. 
If anything else required, please feel free let me know.

Thanks,

Chen

>
>> BTW, what I did this time may be a bit redundant. I would like to ask, if I
>> encounter a similar situation in the future (that is, only one patch needs
>> to be modified, and the others remain unchanged), is there a better way to
>> submit the patchset?
> You could have sent the plic change as a incremental change on top. So a
> new patch with just that one change in it.
>
> Thanks,
> Conor.

On Sat, Oct 07, 2023 at 08:25:55PM +0800, Chen Wang wrote:
> On 2023/10/7 19:04, Conor Dooley wrote:
> > On Sat, Oct 07, 2023 at 06:58:51PM +0800, Chen Wang wrote:
> > > On 2023/10/7 18:17, Conor Dooley wrote:
> > > > On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
> > > > > From: Chen Wang <unicorn_wang@outlook.com>

> > > > > Changes in v5:
> > > > >     The patch series is based on v6.6-rc1. You can simply review or test
> > > > >     the patches at the link [7].
> > > > >     - dts: changed plic to support external interrupt
> > > > >     - pickup improvements from Conor, details refer to [8].
> > > > Did you? I only see them partially picked up. I'll just replace patch 8
> > > > with the patch 8 from this series I think.
> > > Yes, only the patch 8 of this series(v5) is updated for plic node. For other
> > > patches, I just cherry-picked them from previous "sophon" branch.
> > But added my signoff? I ended up seeing my signoff on the patch where I
> > disagreed with the commit message, which was confusing to me.
> 
> Oh, I used to think I can keep the exising signoff and I didn't mean to add
> it.

I added mine when I applied the patches. It no longer makes sense when
you resent another version.

> Anyway, I agree your suggestion to create a new patch with only one
> change should be better, I will follow this in later work.

:)

> Regarding your changes on sg2042 series, I have acked in another email : https://lore.kernel.org/linux-riscv/MA0P287MB0332BA73D0135CC73CAEA16DFEC8A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/.
> If anything else required, please feel free let me know.

An ack on Jisheng's series for the cv1800b would be nice.

On 2023/10/7 20:36, Conor Dooley wrote:
> On Sat, Oct 07, 2023 at 08:25:55PM +0800, Chen Wang wrote:
>> On 2023/10/7 19:04, Conor Dooley wrote:
>>> On Sat, Oct 07, 2023 at 06:58:51PM +0800, Chen Wang wrote:
>>>> On 2023/10/7 18:17, Conor Dooley wrote:
>>>>> On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
>>>>>> From: Chen Wang <unicorn_wang@outlook.com>
>>>>>> Changes in v5:
>>>>>>      The patch series is based on v6.6-rc1. You can simply review or test
>>>>>>      the patches at the link [7].
>>>>>>      - dts: changed plic to support external interrupt
>>>>>>      - pickup improvements from Conor, details refer to [8].
>>>>> Did you? I only see them partially picked up. I'll just replace patch 8
>>>>> with the patch 8 from this series I think.
>>>> Yes, only the patch 8 of this series(v5) is updated for plic node. For other
>>>> patches, I just cherry-picked them from previous "sophon" branch.
>>> But added my signoff? I ended up seeing my signoff on the patch where I
>>> disagreed with the commit message, which was confusing to me.
>> Oh, I used to think I can keep the exising signoff and I didn't mean to add
>> it.
> I added mine when I applied the patches. It no longer makes sense when
> you resent another version.
>
>> Anyway, I agree your suggestion to create a new patch with only one
>> change should be better, I will follow this in later work.
> :)
>
>> Regarding your changes on sg2042 series, I have acked in another email : https://lore.kernel.org/linux-riscv/MA0P287MB0332BA73D0135CC73CAEA16DFEC8A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/.
>> If anything else required, please feel free let me know.
> An ack on Jisheng's series for the cv1800b would be nice.

Done, I have reviewed and acked all the files related to sophgo.

On Sat, Oct 07, 2023 at 08:48:34PM +0800, Chen Wang wrote:
> 
> On 2023/10/7 20:36, Conor Dooley wrote:
> > On Sat, Oct 07, 2023 at 08:25:55PM +0800, Chen Wang wrote:
> > > On 2023/10/7 19:04, Conor Dooley wrote:
> > > > On Sat, Oct 07, 2023 at 06:58:51PM +0800, Chen Wang wrote:
> > > > > On 2023/10/7 18:17, Conor Dooley wrote:
> > > > > > On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
> > > > > > > From: Chen Wang <unicorn_wang@outlook.com>
> > > > > > > Changes in v5:
> > > > > > >      The patch series is based on v6.6-rc1. You can simply review or test
> > > > > > >      the patches at the link [7].
> > > > > > >      - dts: changed plic to support external interrupt
> > > > > > >      - pickup improvements from Conor, details refer to [8].
> > > > > > Did you? I only see them partially picked up. I'll just replace patch 8
> > > > > > with the patch 8 from this series I think.
> > > > > Yes, only the patch 8 of this series(v5) is updated for plic node. For other
> > > > > patches, I just cherry-picked them from previous "sophon" branch.
> > > > But added my signoff? I ended up seeing my signoff on the patch where I
> > > > disagreed with the commit message, which was confusing to me.
> > > Oh, I used to think I can keep the exising signoff and I didn't mean to add
> > > it.
> > I added mine when I applied the patches. It no longer makes sense when
> > you resent another version.
> > 
> > > Anyway, I agree your suggestion to create a new patch with only one
> > > change should be better, I will follow this in later work.
> > :)
> > 
> > > Regarding your changes on sg2042 series, I have acked in another email : https://lore.kernel.org/linux-riscv/MA0P287MB0332BA73D0135CC73CAEA16DFEC8A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/.
> > > If anything else required, please feel free let me know.
> > An ack on Jisheng's series for the cv1800b would be nice.
> 
> Done, I have reviewed and acked all the files related to sophgo.

Cool. Both your and Jisheng's series should end up in linux-next
tomorrow, I've pushed both to the riscv-dt-for-next branch.

Thanks!