On 5/22/23 16:59, Michal Simek wrote:
> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>
> Based on dt-binding "This property should present when there is more than a
> single SPI" that's also case that's why explicitly specify interrupt
> affinity to avoid incorrect usage.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> Changes in v2:
> - Update commit message to remove OS content - reported by Laurent
>
> This avoids the following error upon linux boot:
> armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
> guessing.
>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 02bd75900238..fc5e21bc647c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -164,6 +164,10 @@ pmu {
> <0 144 4>,
> <0 145 4>,
> <0 146 4>;
> + interrupt-affinity = <&cpu0>,
> + <&cpu1>,
> + <&cpu2>,
> + <&cpu3>;
> };
>
> psci {
Applied.
M