arch/arm/boot/dts/axp209.dtsi | 7 +++++++ arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++ arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++ 3 files changed, 19 insertions(+)
This small patch series adds some improvements for the C.H.I.P DTS, enabling bluetooth, exporting the PMIC temperature details via iio-hwmon and finally adding the appropriate base pinmux info for an external MMC card. Jonathan McDowell (3): ARM: dts: sun5i: chip: Enable bluetooth ARM: dts: sun5i: Add port E pinmux settings for mmc2 ARM: dts: axp209: Add iio-hwmon node for internal temperature arch/arm/boot/dts/axp209.dtsi | 7 +++++++ arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++ arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++ 3 files changed, 19 insertions(+) -- 2.39.2
This small patch series adds some improvements for the C.H.I.P DTS, enabling bluetooth, exporting the PMIC temperature details via iio-hwmon and finally adding the appropriate base pinmux info for an external MMC card. As a pre-requisite for the Bluetooth it also adds support to the AXP209 driver for GPIO3, which is the Bluetooth device wakeup line. v2: - Fix missing ; on bluetooth stanza in DTS - Add device/host wake GPIOs for Bluetooth device - Add omit-if-no-ref on the port E pinmux stanza - Rename axp20x_temp to pmic-temp - Add AXP209 GPIO3 support Jonathan McDowell (5): dt-bindings: gpio: Add GPIO3 for AXP209 GPIO binding schema pinctrl: axp209: Add support for GPIO3 on the AXP209 ARM: dts: sun5i: chip: Enable bluetooth ARM: dts: sun5i: Add port E pinmux settings for mmc2 ARM: dts: axp209: Add iio-hwmon node for internal temperature .../bindings/gpio/x-powers,axp209-gpio.yaml | 1 + arch/arm/boot/dts/axp209.dtsi | 7 ++++ arch/arm/boot/dts/sun5i-r8-chip.dts | 6 +++ arch/arm/boot/dts/sun5i.dtsi | 9 ++++ drivers/pinctrl/pinctrl-axp209.c | 42 +++++++++++++++++++ 5 files changed, 65 insertions(+) -- 2.39.2
This small patch series adds some improvements for the C.H.I.P DTS, enabling bluetooth, exporting the PMIC temperature details via iio-hwmon and finally adding the appropriate base pinmux info for an external MMC card. As a pre-requisite for the Bluetooth it also adds support to the AXP209 driver for GPIO3, which is the Bluetooth device wakeup line. v3: - Add Reviewed-By/Acked-Bys - Drop redundant else - Switch to GENMASK/decimal values for GPIO3 function defs v2: - Fix missing ; on bluetooth stanza in DTS - Add device/host wake GPIOs for Bluetooth device - Add omit-if-no-ref on the port E pinmux stanza - Rename axp20x_temp to pmic-temp - Add AXP209 GPIO3 support Jonathan McDowell (5): dt-bindings: gpio: Add GPIO3 for AXP209 GPIO binding schema pinctrl: axp209: Add support for GPIO3 on the AXP209 ARM: dts: sun5i: chip: Enable bluetooth ARM: dts: sun5i: Add port E pinmux settings for mmc2 ARM: dts: axp209: Add iio-hwmon node for internal temperature .../bindings/gpio/x-powers,axp209-gpio.yaml | 1 + arch/arm/boot/dts/axp209.dtsi | 7 ++++ arch/arm/boot/dts/sun5i-r8-chip.dts | 6 +++ arch/arm/boot/dts/sun5i.dtsi | 9 ++++ drivers/pinctrl/pinctrl-axp209.c | 42 +++++++++++++++++++ 5 files changed, 65 insertions(+) -- 2.39.2
The AXP209 has a 4th GPIO, so add it in preparation for support in the
driver.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml b/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
index 31906c253940..1638cfe90f1c 100644
--- a/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
@@ -44,6 +44,7 @@ patternProperties:
- GPIO0
- GPIO1
- GPIO2
+ - GPIO3
function:
enum:
--
2.39.2On Tue, May 16, 2023 at 7:47 PM Jonathan McDowell <noodles@earth.li> wrote: > > The AXP209 has a 4th GPIO, so add it in preparation for support in the > driver. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> > Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml b/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml > index 31906c253940..1638cfe90f1c 100644 > --- a/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml > @@ -44,6 +44,7 @@ patternProperties: > - GPIO0 > - GPIO1 > - GPIO2 > + - GPIO3 > > function: > enum: > -- > 2.39.2 > Applied, thanks! Bart
On Tue, May 16, 2023 at 7:47 PM Jonathan McDowell <noodles@earth.li> wrote: > The AXP209 has a 4th GPIO, so add it in preparation for support in the > driver. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> > Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
The AXP209 device has a 4th GPIO which has a slightly different register
setup, where the control + status bits are held in a single register
rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
drivers/pinctrl/pinctrl-axp209.c | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
index 0bc1b381a2b8..b3ba25435c34 100644
--- a/drivers/pinctrl/pinctrl-axp209.c
+++ b/drivers/pinctrl/pinctrl-axp209.c
@@ -30,6 +30,11 @@
#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
#define AXP20X_GPIO_FUNCTION_INPUT 2
+#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
+#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
+#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
+#define AXP20X_GPIO3_FUNCTION_INPUT 4
+
#define AXP20X_FUNC_GPIO_OUT 0
#define AXP20X_FUNC_GPIO_IN 1
#define AXP20X_FUNC_LDO 2
@@ -73,6 +78,7 @@ static const struct pinctrl_pin_desc axp209_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
PINCTRL_PIN(2, "GPIO2"),
+ PINCTRL_PIN(3, "GPIO3"),
};
static const struct pinctrl_pin_desc axp22x_pins[] = {
@@ -130,6 +136,14 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
unsigned int val;
int ret;
+ /* AXP209 has GPIO3 status sharing the settings register */
+ if (offset == 3) {
+ ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
+ if (ret)
+ return ret;
+ return !!(val & BIT(0));
+ }
+
ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
if (ret)
return ret;
@@ -144,6 +158,17 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip,
unsigned int val;
int reg, ret;
+ /* AXP209 GPIO3 settings have a different layout */
+ if (offset == 3) {
+ ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
+ if (ret)
+ return ret;
+ if (val & AXP20X_GPIO3_FUNCTION_INPUT)
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
+ }
+
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
@@ -184,6 +209,15 @@ static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
int reg;
+ /* AXP209 has GPIO3 status sharing the settings register */
+ if (offset == 3) {
+ regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
+ AXP20X_GPIO3_FUNCTIONS,
+ value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
+ AXP20X_GPIO3_FUNCTION_OUT_LOW);
+ return;
+ }
+
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return;
@@ -200,6 +234,14 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
int reg;
+ /* AXP209 GPIO3 settings have a different layout */
+ if (offset == 3) {
+ return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
+ AXP20X_GPIO3_FUNCTIONS,
+ config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
+ AXP20X_GPIO3_FUNCTION_INPUT);
+ }
+
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
--
2.39.2Dne torek, 16. maj 2023 ob 19:47:29 CEST je Jonathan McDowell napisal(a):
> The AXP209 device has a 4th GPIO which has a slightly different register
> setup, where the control + status bits are held in a single register
> rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2.
>
> Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
> ---
> drivers/pinctrl/pinctrl-axp209.c | 42 ++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
> index 0bc1b381a2b8..b3ba25435c34 100644
> --- a/drivers/pinctrl/pinctrl-axp209.c
> +++ b/drivers/pinctrl/pinctrl-axp209.c
> @@ -30,6 +30,11 @@
> #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
> #define AXP20X_GPIO_FUNCTION_INPUT 2
>
> +#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
> +#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
> +#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
> +#define AXP20X_GPIO3_FUNCTION_INPUT 4
> +
> #define AXP20X_FUNC_GPIO_OUT 0
> #define AXP20X_FUNC_GPIO_IN 1
> #define AXP20X_FUNC_LDO 2
> @@ -73,6 +78,7 @@ static const struct pinctrl_pin_desc axp209_pins[] = {
> PINCTRL_PIN(0, "GPIO0"),
> PINCTRL_PIN(1, "GPIO1"),
> PINCTRL_PIN(2, "GPIO2"),
> + PINCTRL_PIN(3, "GPIO3"),
> };
>
> static const struct pinctrl_pin_desc axp22x_pins[] = {
> @@ -130,6 +136,14 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
> unsigned int val;
> int ret;
>
> + /* AXP209 has GPIO3 status sharing the settings register */
> + if (offset == 3) {
> + ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
> + if (ret)
> + return ret;
> + return !!(val & BIT(0));
> + }
> +
> ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
> if (ret)
> return ret;
> @@ -144,6 +158,17 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip,
> unsigned int val;
> int reg, ret;
>
> + /* AXP209 GPIO3 settings have a different layout */
> + if (offset == 3) {
> + ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
> + if (ret)
> + return ret;
> + if (val & AXP20X_GPIO3_FUNCTION_INPUT)
> + return GPIO_LINE_DIRECTION_IN;
> +
> + return GPIO_LINE_DIRECTION_OUT;
> + }
> +
> reg = axp20x_gpio_get_reg(offset);
> if (reg < 0)
> return reg;
> @@ -184,6 +209,15 @@ static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
> struct axp20x_pctl *pctl = gpiochip_get_data(chip);
> int reg;
>
> + /* AXP209 has GPIO3 status sharing the settings register */
> + if (offset == 3) {
> + regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
> + AXP20X_GPIO3_FUNCTIONS,
> + value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
> + AXP20X_GPIO3_FUNCTION_OUT_LOW);
> + return;
> + }
> +
> reg = axp20x_gpio_get_reg(offset);
> if (reg < 0)
> return;
> @@ -200,6 +234,14 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
> struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
> int reg;
>
> + /* AXP209 GPIO3 settings have a different layout */
> + if (offset == 3) {
> + return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
> + AXP20X_GPIO3_FUNCTIONS,
> + config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
> + AXP20X_GPIO3_FUNCTION_INPUT);
> + }
> +
> reg = axp20x_gpio_get_reg(offset);
> if (reg < 0)
> return reg;
>
On Tue, May 16, 2023 at 8:47 PM Jonathan McDowell <noodles@earth.li> wrote:
>
> The AXP209 device has a 4th GPIO which has a slightly different register
> setup, where the control + status bits are held in a single register
> rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2.
LGTM,
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Signed-off-by: Jonathan McDowell <noodles@earth.li>
> ---
> drivers/pinctrl/pinctrl-axp209.c | 42 ++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
> index 0bc1b381a2b8..b3ba25435c34 100644
> --- a/drivers/pinctrl/pinctrl-axp209.c
> +++ b/drivers/pinctrl/pinctrl-axp209.c
> @@ -30,6 +30,11 @@
> #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
> #define AXP20X_GPIO_FUNCTION_INPUT 2
>
> +#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
> +#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
> +#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
> +#define AXP20X_GPIO3_FUNCTION_INPUT 4
> +
> #define AXP20X_FUNC_GPIO_OUT 0
> #define AXP20X_FUNC_GPIO_IN 1
> #define AXP20X_FUNC_LDO 2
> @@ -73,6 +78,7 @@ static const struct pinctrl_pin_desc axp209_pins[] = {
> PINCTRL_PIN(0, "GPIO0"),
> PINCTRL_PIN(1, "GPIO1"),
> PINCTRL_PIN(2, "GPIO2"),
> + PINCTRL_PIN(3, "GPIO3"),
> };
>
> static const struct pinctrl_pin_desc axp22x_pins[] = {
> @@ -130,6 +136,14 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
> unsigned int val;
> int ret;
>
> + /* AXP209 has GPIO3 status sharing the settings register */
> + if (offset == 3) {
> + ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
> + if (ret)
> + return ret;
> + return !!(val & BIT(0));
> + }
> +
> ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
> if (ret)
> return ret;
> @@ -144,6 +158,17 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip,
> unsigned int val;
> int reg, ret;
>
> + /* AXP209 GPIO3 settings have a different layout */
> + if (offset == 3) {
> + ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
> + if (ret)
> + return ret;
> + if (val & AXP20X_GPIO3_FUNCTION_INPUT)
> + return GPIO_LINE_DIRECTION_IN;
> +
> + return GPIO_LINE_DIRECTION_OUT;
> + }
> +
> reg = axp20x_gpio_get_reg(offset);
> if (reg < 0)
> return reg;
> @@ -184,6 +209,15 @@ static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
> struct axp20x_pctl *pctl = gpiochip_get_data(chip);
> int reg;
>
> + /* AXP209 has GPIO3 status sharing the settings register */
> + if (offset == 3) {
> + regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
> + AXP20X_GPIO3_FUNCTIONS,
> + value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
> + AXP20X_GPIO3_FUNCTION_OUT_LOW);
> + return;
> + }
> +
> reg = axp20x_gpio_get_reg(offset);
> if (reg < 0)
> return;
> @@ -200,6 +234,14 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
> struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
> int reg;
>
> + /* AXP209 GPIO3 settings have a different layout */
> + if (offset == 3) {
> + return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
> + AXP20X_GPIO3_FUNCTIONS,
> + config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
> + AXP20X_GPIO3_FUNCTION_INPUT);
> + }
> +
> reg = axp20x_gpio_get_reg(offset);
> if (reg < 0)
> return reg;
> --
> 2.39.2
>
--
With Best Regards,
Andy Shevchenko
The C.H.I.P has an rtl8723bs device with the bluetooth interface hooked
up on UART3. Support for this didn't exist in mainline when the DTS was
initially added, but it does now, so enable it.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index fd37bd1f3920..4192c23848c3 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -255,6 +255,12 @@ &uart3 {
pinctrl-0 = <&uart3_pg_pins>,
<&uart3_cts_rts_pg_pins>;
status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ };
};
&usb_otg {
--
2.39.2These alternate pins for mmc2 are brought out to the 40 pin U14 header
on the C.H.I.P and can be used to add an external MMC device with a 4
bit interface. See
https://byteporter.com/ntc-chip-micro-sd-slot/
for further details on how.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/boot/dts/sun5i.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 250d6b87ab4d..ab7f675aeec4 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -517,6 +517,15 @@ mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
bias-pull-up;
};
+ /omit-if-no-ref/
+ mmc2_4bit_pe_pins: mmc2-4bit-pe-pins {
+ pins = "PE4", "PE5", "PE6", "PE7",
+ "PE8", "PE9";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13",
--
2.39.2This adds a DT node to hook up the internal temperature ADC to the
iio-hwmon driver. The various voltage + current ADCs are consumed and
exposed by their respective drivers, but this is not and is always
available. Naming chosen to match the axp20x_ prefix the power sensors
use.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/boot/dts/axp209.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
index ca240cd6f6c3..469d0f7d5185 100644
--- a/arch/arm/boot/dts/axp209.dtsi
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -48,6 +48,13 @@
* http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
*/
+/ {
+ pmic-temp {
+ compatible = "iio-hwmon";
+ io-channels = <&axp_adc 4>; /* Internal temperature */
+ };
+};
+
&axp209 {
compatible = "x-powers,axp209";
interrupt-controller;
--
2.39.2The AXP209 has a 4th GPIO, so add it in preparation for support in the
driver.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml b/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
index 31906c253940..1638cfe90f1c 100644
--- a/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
@@ -44,6 +44,7 @@ patternProperties:
- GPIO0
- GPIO1
- GPIO2
+ - GPIO3
function:
enum:
--
2.39.2On Wed, May 10, 2023 at 01:01:12PM +0100, Jonathan McDowell wrote: > The AXP209 has a 4th GPIO, so add it in preparation for support in the > driver. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> Acked-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
Dne sreda, 10. maj 2023 ob 14:01:12 CEST je Jonathan McDowell napisal(a): > The AXP209 has a 4th GPIO, so add it in preparation for support in the > driver. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
The AXP209 device has a 4th GPIO which has a slightly different register
setup, where the control + status bits are held in a single register
rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
drivers/pinctrl/pinctrl-axp209.c | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
index 0bc1b381a2b8..317691aee86b 100644
--- a/drivers/pinctrl/pinctrl-axp209.c
+++ b/drivers/pinctrl/pinctrl-axp209.c
@@ -30,6 +30,11 @@
#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
#define AXP20X_GPIO_FUNCTION_INPUT 2
+#define AXP20X_GPIO3_FUNCTIONS (BIT(2) | BIT(1))
+#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
+#define AXP20X_GPIO3_FUNCTION_OUT_HIGH BIT(1)
+#define AXP20X_GPIO3_FUNCTION_INPUT BIT(2)
+
#define AXP20X_FUNC_GPIO_OUT 0
#define AXP20X_FUNC_GPIO_IN 1
#define AXP20X_FUNC_LDO 2
@@ -73,6 +78,7 @@ static const struct pinctrl_pin_desc axp209_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
PINCTRL_PIN(2, "GPIO2"),
+ PINCTRL_PIN(3, "GPIO3"),
};
static const struct pinctrl_pin_desc axp22x_pins[] = {
@@ -130,6 +136,14 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
unsigned int val;
int ret;
+ /* AXP209 has GPIO3 status sharing the settings register */
+ if (offset == 3) {
+ ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
+ if (ret)
+ return ret;
+ return !!(val & BIT(0));
+ }
+
ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
if (ret)
return ret;
@@ -144,6 +158,17 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip,
unsigned int val;
int reg, ret;
+ /* AXP209 GPIO3 settings have a different layout */
+ if (offset == 3) {
+ ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
+ if (ret)
+ return ret;
+ if (val & AXP20X_GPIO3_FUNCTION_INPUT)
+ return GPIO_LINE_DIRECTION_IN;
+ else
+ return GPIO_LINE_DIRECTION_OUT;
+ }
+
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
@@ -184,6 +209,15 @@ static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
int reg;
+ /* AXP209 has GPIO3 status sharing the settings register */
+ if (offset == 3) {
+ regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
+ AXP20X_GPIO3_FUNCTIONS,
+ value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
+ AXP20X_GPIO3_FUNCTION_OUT_LOW);
+ return;
+ }
+
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return;
@@ -200,6 +234,14 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
int reg;
+ /* AXP209 GPIO3 settings have a different layout */
+ if (offset == 3) {
+ return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
+ AXP20X_GPIO3_FUNCTIONS,
+ config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
+ AXP20X_GPIO3_FUNCTION_INPUT);
+ }
+
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
--
2.39.2On Wed, May 10, 2023 at 2:01 PM Jonathan McDowell <noodles@earth.li> wrote: > The AXP209 device has a 4th GPIO which has a slightly different register > setup, where the control + status bits are held in a single register > rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> This patch 2/5 applied to the pinctrl tree. I just assume it is fine to apply this one patch, Bartosz already applied the binding patch. Tell me if this works. Yours, Linus Walleij
On Mon, May 29, 2023 at 11:51:46AM +0200, Linus Walleij wrote: > On Wed, May 10, 2023 at 2:01 PM Jonathan McDowell <noodles@earth.li> wrote: > > The AXP209 device has a 4th GPIO which has a slightly different register > > setup, where the control + status bits are held in a single register > > rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2. > > > > Signed-off-by: Jonathan McDowell <noodles@earth.li> > > This patch 2/5 applied to the pinctrl tree. > > I just assume it is fine to apply this one patch, Bartosz already > applied the binding patch. > > Tell me if this works. Everything else seems to have been picked up, so that works for me. J. -- Revd Jonathan McDowell, ULC | Even the Evening Herald slags me off.
Wed, May 10, 2023 at 01:01:27PM +0100, Jonathan McDowell kirjoitti:
> The AXP209 device has a 4th GPIO which has a slightly different register
> setup, where the control + status bits are held in a single register
> rather than sharing AXP20X_GPIO20_SS with GPIOs 0-2.
...
> +#define AXP20X_GPIO3_FUNCTIONS (BIT(2) | BIT(1))
GENMASK() ?
...
> +#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
> +#define AXP20X_GPIO3_FUNCTION_OUT_HIGH BIT(1)
> +#define AXP20X_GPIO3_FUNCTION_INPUT BIT(2)
Seems mixed use of decimal and bitwise values, switch to decimal, since it
makes more sense in my opinion.
...
> + if (offset == 3) {
> + ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
> + if (ret)
> + return ret;
> + if (val & AXP20X_GPIO3_FUNCTION_INPUT)
> + return GPIO_LINE_DIRECTION_IN;
> + else
Redundant 'else'.
> + return GPIO_LINE_DIRECTION_OUT;
> + }
--
With Best Regards,
Andy Shevchenko
The C.H.I.P has an rtl8723bs device with the bluetooth interface hooked
up on UART3. Support for this didn't exist in mainline when the DTS was
initially added, but it does now, so enable it.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index fd37bd1f3920..4192c23848c3 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -255,6 +255,12 @@ &uart3 {
pinctrl-0 = <&uart3_pg_pins>,
<&uart3_cts_rts_pg_pins>;
status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ };
};
&usb_otg {
--
2.39.2Dne sreda, 10. maj 2023 ob 14:01:43 CEST je Jonathan McDowell napisal(a): > The C.H.I.P has an rtl8723bs device with the bluetooth interface hooked > up on UART3. Support for this didn't exist in mainline when the DTS was > initially added, but it does now, so enable it. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
These alternate pins for mmc2 are brought out to the 40 pin U14 header
on the C.H.I.P and can be used to add an external MMC device with a 4
bit interface. See
https://byteporter.com/ntc-chip-micro-sd-slot/
for further details on how.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/sun5i.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 250d6b87ab4d..ab7f675aeec4 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -517,6 +517,15 @@ mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
bias-pull-up;
};
+ /omit-if-no-ref/
+ mmc2_4bit_pe_pins: mmc2-4bit-pe-pins {
+ pins = "PE4", "PE5", "PE6", "PE7",
+ "PE8", "PE9";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13",
--
2.39.2Dne sreda, 10. maj 2023 ob 14:02:02 CEST je Jonathan McDowell napisal(a): > These alternate pins for mmc2 are brought out to the 40 pin U14 header > on the C.H.I.P and can be used to add an external MMC device with a 4 > bit interface. See > > https://byteporter.com/ntc-chip-micro-sd-slot/ > > for further details on how. > > Signed-off-by: Jonathan McDowell <noodles@earth.li> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
This adds a DT node to hook up the internal temperature ADC to the
iio-hwmon driver. The various voltage + current ADCs are consumed and
exposed by their respective drivers, but this is not and is always
available. Naming chosen to match the axp20x_ prefix the power sensors
use.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/axp209.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
index ca240cd6f6c3..469d0f7d5185 100644
--- a/arch/arm/boot/dts/axp209.dtsi
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -48,6 +48,13 @@
* http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
*/
+/ {
+ pmic-temp {
+ compatible = "iio-hwmon";
+ io-channels = <&axp_adc 4>; /* Internal temperature */
+ };
+};
+
&axp209 {
compatible = "x-powers,axp209";
interrupt-controller;
--
2.39.2Dne sreda, 10. maj 2023 ob 14:02:28 CEST je Jonathan McDowell napisal(a):
> This adds a DT node to hook up the internal temperature ADC to the
> iio-hwmon driver. The various voltage + current ADCs are consumed and
> exposed by their respective drivers, but this is not and is always
> available. Naming chosen to match the axp20x_ prefix the power sensors
> use.
Sorry for maybe obvious thing, but where are other ADC channels exposed?
Best regards,
Jernej
>
> Signed-off-by: Jonathan McDowell <noodles@earth.li>
> ---
> arch/arm/boot/dts/axp209.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
> index ca240cd6f6c3..469d0f7d5185 100644
> --- a/arch/arm/boot/dts/axp209.dtsi
> +++ b/arch/arm/boot/dts/axp209.dtsi
> @@ -48,6 +48,13 @@
> * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
> */
>
> +/ {
> + pmic-temp {
> + compatible = "iio-hwmon";
> + io-channels = <&axp_adc 4>; /* Internal temperature */
> + };
> +};
> +
> &axp209 {
> compatible = "x-powers,axp209";
> interrupt-controller;
On Thu, May 11, 2023 at 06:11:49PM +0200, Jernej Škrabec wrote:
> Dne sreda, 10. maj 2023 ob 14:02:28 CEST je Jonathan McDowell napisal(a):
> > This adds a DT node to hook up the internal temperature ADC to the
> > iio-hwmon driver. The various voltage + current ADCs are consumed and
> > exposed by their respective drivers, but this is not and is always
> > available. Naming chosen to match the axp20x_ prefix the power sensors
> > use.
>
> Sorry for maybe obvious thing, but where are other ADC channels exposed?
In the associated power drivers; e.g. axp20x_ac_power, axp20x_usb_power
+ axp20x_battery. The internal temperature is the only one that
logically belongs to the chip as a whole rather than one of the
subfunctions.
root@chip:~# sensors
axp20x_battery-isa-0000
Adapter: ISA adapter
in0: 0.00 V
curr1: 0.00 A
pmic_temp-isa-0000
Adapter: ISA adapter
temp1: +42.5°C
axp20x_ac-isa-0000
Adapter: ISA adapter
in0: 0.00 V
curr1: 0.00 A
axp20x_usb-isa-0000
Adapter: ISA adapter
in0: 4.93 V (min = +4.00 V)
curr1: 330.00 mA (max = +0.00 A)
> > Signed-off-by: Jonathan McDowell <noodles@earth.li>
> > ---
> > arch/arm/boot/dts/axp209.dtsi | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
> > index ca240cd6f6c3..469d0f7d5185 100644
> > --- a/arch/arm/boot/dts/axp209.dtsi
> > +++ b/arch/arm/boot/dts/axp209.dtsi
> > @@ -48,6 +48,13 @@
> > * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
> > */
> >
> > +/ {
> > + pmic-temp {
> > + compatible = "iio-hwmon";
> > + io-channels = <&axp_adc 4>; /* Internal temperature */
> > + };
> > +};
> > +
> > &axp209 {
> > compatible = "x-powers,axp209";
> > interrupt-controller;
J.
--
/-\ | Synonym: word used when you can't
|@/ Debian GNU/Linux Developer | spell the one you want
\- |
Dne petek, 12. maj 2023 ob 12:30:32 CEST je Jonathan McDowell napisal(a):
> On Thu, May 11, 2023 at 06:11:49PM +0200, Jernej Škrabec wrote:
> > Dne sreda, 10. maj 2023 ob 14:02:28 CEST je Jonathan McDowell napisal(a):
> > > This adds a DT node to hook up the internal temperature ADC to the
> > > iio-hwmon driver. The various voltage + current ADCs are consumed and
> > > exposed by their respective drivers, but this is not and is always
> > > available. Naming chosen to match the axp20x_ prefix the power sensors
> > > use.
> >
> > Sorry for maybe obvious thing, but where are other ADC channels exposed?
>
> In the associated power drivers; e.g. axp20x_ac_power, axp20x_usb_power
> + axp20x_battery. The internal temperature is the only one that
> logically belongs to the chip as a whole rather than one of the
> subfunctions.
>
> root@chip:~# sensors
> axp20x_battery-isa-0000
> Adapter: ISA adapter
> in0: 0.00 V
> curr1: 0.00 A
>
> pmic_temp-isa-0000
> Adapter: ISA adapter
> temp1: +42.5°C
>
> axp20x_ac-isa-0000
> Adapter: ISA adapter
> in0: 0.00 V
> curr1: 0.00 A
>
> axp20x_usb-isa-0000
> Adapter: ISA adapter
> in0: 4.93 V (min = +4.00 V)
> curr1: 330.00 mA (max = +0.00 A)
Right.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
>
> > > Signed-off-by: Jonathan McDowell <noodles@earth.li>
> > > ---
> > >
> > > arch/arm/boot/dts/axp209.dtsi | 7 +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/axp209.dtsi
> > > b/arch/arm/boot/dts/axp209.dtsi
> > > index ca240cd6f6c3..469d0f7d5185 100644
> > > --- a/arch/arm/boot/dts/axp209.dtsi
> > > +++ b/arch/arm/boot/dts/axp209.dtsi
> > > @@ -48,6 +48,13 @@
> > >
> > > * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
> > > */
> > >
> > > +/ {
> > > + pmic-temp {
> > > + compatible = "iio-hwmon";
> > > + io-channels = <&axp_adc 4>; /* Internal temperature */
> > > + };
> > > +};
> > > +
> > >
> > > &axp209 {
> > >
> > > compatible = "x-powers,axp209";
> > > interrupt-controller;
>
> J.
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