ADC sample captures take a certain amount of time to complete after
initiated; this conversion time range can be anywhere from 5 uSec to
53.68 Seconds depending on the configuration of the Analog Input Frame
Timer register. When the conversion is in progress, the ADC Status
register CNV bit is high. Utilize regmap_read_poll_timeout() to poll
until the ADC conversion is completed (or timeout if more than 53.68
Seconds passes).

Suggested-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
---
Changes in v4: none

 drivers/iio/addac/stx104.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c
index f300cce52787..0cdb824b6bb6 100644
--- a/drivers/iio/addac/stx104.c
+++ b/drivers/iio/addac/stx104.c
@@ -206,19 +206,22 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
 
 		/* trigger ADC sample capture by writing to the 8-bit
 		 * Software Strobe Register and wait for completion
+		 * Range is 5 uSec to 53.68 Seconds in steps of 25 nanoseconds.
+		 * The actual Analog Input Frame Timer time interval is calculated as:
+		 * ai_time_frame_ns = ( AIFT + 1 ) * ( 25 nSec ).
+		 * Where 0 <= AIFT <= 2147483648.
 		 */
 		err = regmap_write(priv->aio_ctl_map, STX104_SOFTWARE_STROBE, 0);
 		if (err) {
 			mutex_unlock(&priv->lock);
 			return err;
 		}
-		do {
-			err = regmap_read(priv->aio_ctl_map, STX104_ADC_STATUS, &adc_status);
-			if (err) {
-				mutex_unlock(&priv->lock);
-				return err;
-			}
-		} while (u8_get_bits(adc_status, STX104_CNV));
+		err = regmap_read_poll_timeout(priv->aio_ctl_map, STX104_ADC_STATUS, adc_status,
+					       !u8_get_bits(adc_status, STX104_CNV), 0, 53687092);
+		if (err) {
+			mutex_unlock(&priv->lock);
+			return err;
+		}
 
 		err = regmap_read(priv->aio_data_map, STX104_ADC_DATA, &value);
 		if (err) {
-- 
2.39.2

On Tue, Apr 04, 2023 at 10:12:02AM -0400, William Breathitt Gray wrote:
> ADC sample captures take a certain amount of time to complete after
> initiated; this conversion time range can be anywhere from 5 uSec to
> 53.68 Seconds depending on the configuration of the Analog Input Frame
> Timer register. When the conversion is in progress, the ADC Status
> register CNV bit is high. Utilize regmap_read_poll_timeout() to poll
> until the ADC conversion is completed (or timeout if more than 53.68
> Seconds passes).

...

>  		/* trigger ADC sample capture by writing to the 8-bit

Perhaps fix the style here while at it?

		/*
		 * Trigger ADC sample capture by writing to the 8-bit

>  		 * Software Strobe Register and wait for completion
> +		 * Range is 5 uSec to 53.68 Seconds in steps of 25 nanoseconds.

seconds (in SI the small letter is for the unit(s) of seconds).

Same for the commit message.

> +		 * The actual Analog Input Frame Timer time interval is calculated as:
> +		 * ai_time_frame_ns = ( AIFT + 1 ) * ( 25 nSec ).

nSec --> nanosecond

> +		 * Where 0 <= AIFT <= 2147483648.
>  		 */

-- 
With Best Regards,
Andy Shevchenko