Add USB phy and controller related nodes
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since
ipq9574 doesn't have power domains. Hope this is ok
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues
Changes in v3:
- Insert the nodes at proper location
Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper
interconnect support)
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2bb4053..8fa9e1a 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -186,6 +186,33 @@
method = "smc";
};
+ reg_usb_3p3: s3300 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "usb-phy-vdd-dummy";
+ };
+
+ reg_usb_1p8: s1800 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "usb-phy-pll-dummy";
+ };
+
+ reg_usb_0p925: s0925 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "usb-phy-dummy";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -215,6 +242,52 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ qusb_phy_0: phy@7b000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x0007b000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ vdd-supply = <®_usb_0p925>;
+ vdda-pll-supply = <®_usb_1p8>;
+ vdda-phy-dpdm-supply = <®_usb_3p3>;
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@7d000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x0007d000 0xa00>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&xo_board_clk>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ vdda-pll-supply = <®_usb_1p8>;
+ vdda-phy-supply = <®_usb_0p925>;
+
+ status = "disabled";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb0_pipe_clk";
+ };
+
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1bc>; /* Serdes PLL */
@@ -436,6 +509,53 @@
status = "disabled";
};
+ usb3: usb@8a00000 {
+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "sys_noc_axi",
+ "anoc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event";
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.7.4On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> Changes in v5:
> - Fix additional comments
> - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> - 'make dtbs_check' giving the following messages since
> ipq9574 doesn't have power domains. Hope this is ok
>
> /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
No, I think it is not.
>
>
> Changes in v4:
> - Use newer bindings without subnodes
> - Fix coding style issues
>
> Changes in v3:
> - Insert the nodes at proper location
>
> Changes in v2:
> - Fixed issues flagged by Krzysztof
> - Fix issues reported by make dtbs_check
> - Remove NOC related clocks (to be added with proper
> interconnect support)
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
> 1 file changed, 120 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..8fa9e1a 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -186,6 +186,33 @@
> method = "smc";
> };
>
> + reg_usb_3p3: s3300 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-name = "usb-phy-vdd-dummy";
> + };
> +
> + reg_usb_1p8: s1800 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-name = "usb-phy-pll-dummy";
> + };
> +
> + reg_usb_0p925: s0925 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <925000>;
> + regulator-max-microvolt = <925000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-name = "usb-phy-dummy";
> + };
> +
> reserved-memory {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -215,6 +242,52 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + qusb_phy_0: phy@7b000 {
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x0007b000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + vdd-supply = <®_usb_0p925>;
> + vdda-pll-supply = <®_usb_1p8>;
> + vdda-phy-dpdm-supply = <®_usb_3p3>;
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + ssphy_0: phy@7d000 {
Nit: usually the label usb_0_qmpphy
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x0007d000 0xa00>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&xo_board_clk>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "pipe";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy",
> + "phy_phy";
> +
> + vdda-pll-supply = <®_usb_1p8>;
> + vdda-phy-supply = <®_usb_0p925>;
> +
> + status = "disabled";
> +
> + #clock-cells = <0>;
> + clock-output-names = "usb0_pipe_clk";
> + };
> +
> pcie0_phy: phy@84000 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> @@ -436,6 +509,53 @@
> status = "disabled";
> };
>
> + usb3: usb@8a00000 {
> + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> + reg = <0x08af8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <24000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event";
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: usb@8a00000 {
> + compatible = "snps,dwc3";
> + reg = <0x8a00000 0xcd00>;
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + clock-names = "ref";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&qusb_phy_0>, <&ssphy_0>;
> + phy-names = "usb2-phy", "usb3-phy";
> + tx-fifo-resize;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + dr_mode = "host";
> + };
> + };
> +
> intc: interrupt-controller@b000000 {
> compatible = "qcom,msm-qgic2";
> reg = <0x0b000000 0x1000>, /* GICD */
> --
> 2.7.4
>
--
With best wishes
Dmitry
On Thu, Mar 30, 2023 at 12:44:40PM +0300, Dmitry Baryshkov wrote:
> On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > Add USB phy and controller related nodes
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > Changes in v5:
> > - Fix additional comments
> > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > - 'make dtbs_check' giving the following messages since
> > ipq9574 doesn't have power domains. Hope this is ok
> >
> > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>
> No, I think it is not.
There are no GDSCs in IPQ9574. Can you suggest how to proceed.
Thanks
Varada
> > Changes in v4:
> > - Use newer bindings without subnodes
> > - Fix coding style issues
> >
> > Changes in v3:
> > - Insert the nodes at proper location
> >
> > Changes in v2:
> > - Fixed issues flagged by Krzysztof
> > - Fix issues reported by make dtbs_check
> > - Remove NOC related clocks (to be added with proper
> > interconnect support)
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 120 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 2bb4053..8fa9e1a 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -186,6 +186,33 @@
> > method = "smc";
> > };
> >
> > + reg_usb_3p3: s3300 {
> > + compatible = "regulator-fixed";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-name = "usb-phy-vdd-dummy";
> > + };
> > +
> > + reg_usb_1p8: s1800 {
> > + compatible = "regulator-fixed";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-name = "usb-phy-pll-dummy";
> > + };
> > +
> > + reg_usb_0p925: s0925 {
> > + compatible = "regulator-fixed";
> > + regulator-min-microvolt = <925000>;
> > + regulator-max-microvolt = <925000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-name = "usb-phy-dummy";
> > + };
> > +
> > reserved-memory {
> > #address-cells = <2>;
> > #size-cells = <2>;
> > @@ -215,6 +242,52 @@
> > #size-cells = <1>;
> > ranges = <0 0 0 0xffffffff>;
> >
> > + qusb_phy_0: phy@7b000 {
> > + compatible = "qcom,ipq9574-qusb2-phy";
> > + reg = <0x0007b000 0x180>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > + <&xo_board_clk>;
> > + clock-names = "cfg_ahb",
> > + "ref";
> > +
> > + vdd-supply = <®_usb_0p925>;
> > + vdda-pll-supply = <®_usb_1p8>;
> > + vdda-phy-dpdm-supply = <®_usb_3p3>;
> > +
> > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > + status = "disabled";
> > + };
> > +
> > + ssphy_0: phy@7d000 {
>
> Nit: usually the label usb_0_qmpphy
>
> > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > + reg = <0x0007d000 0xa00>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > + <&xo_board_clk>,
> > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > + <&gcc GCC_USB0_PIPE_CLK>;
> > + clock-names = "aux",
> > + "ref",
> > + "com_aux",
> > + "pipe";
> > +
> > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > + reset-names = "phy",
> > + "phy_phy";
> > +
> > + vdda-pll-supply = <®_usb_1p8>;
> > + vdda-phy-supply = <®_usb_0p925>;
> > +
> > + status = "disabled";
> > +
> > + #clock-cells = <0>;
> > + clock-output-names = "usb0_pipe_clk";
> > + };
> > +
> > pcie0_phy: phy@84000 {
> > compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> > reg = <0x00084000 0x1bc>; /* Serdes PLL */
> > @@ -436,6 +509,53 @@
> > status = "disabled";
> > };
> >
> > + usb3: usb@8a00000 {
> > + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> > + reg = <0x08af8800 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + clocks = <&gcc GCC_SNOC_USB_CLK>,
> > + <&gcc GCC_ANOC_USB_AXI_CLK>,
> > + <&gcc GCC_USB0_MASTER_CLK>,
> > + <&gcc GCC_USB0_SLEEP_CLK>,
> > + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +
> > + clock-names = "sys_noc_axi",
> > + "anoc_axi",
> > + "master",
> > + "sleep",
> > + "mock_utmi";
> > +
> > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > + assigned-clock-rates = <200000000>,
> > + <24000000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pwr_event";
> > +
> > + resets = <&gcc GCC_USB_BCR>;
> > + status = "disabled";
> > +
> > + dwc_0: usb@8a00000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x8a00000 0xcd00>;
> > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > + clock-names = "ref";
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&qusb_phy_0>, <&ssphy_0>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > + tx-fifo-resize;
> > + snps,is-utmi-l1-suspend;
> > + snps,hird-threshold = /bits/ 8 <0x0>;
> > + snps,dis_u2_susphy_quirk;
> > + snps,dis_u3_susphy_quirk;
> > + dr_mode = "host";
> > + };
> > + };
> > +
> > intc: interrupt-controller@b000000 {
> > compatible = "qcom,msm-qgic2";
> > reg = <0x0b000000 0x1000>, /* GICD */
> > --
> > 2.7.4
> >
>
>
> --
> With best wishes
> Dmitry
On Fri, Mar 31, 2023 at 02:57:11PM +0530, Varadarajan Narayanan wrote:
> On Thu, Mar 30, 2023 at 12:44:40PM +0300, Dmitry Baryshkov wrote:
> > On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> > <quic_varada@quicinc.com> wrote:
> > >
> > > Add USB phy and controller related nodes
> > >
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > > Changes in v5:
> > > - Fix additional comments
> > > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > - 'make dtbs_check' giving the following messages since
> > > ipq9574 doesn't have power domains. Hope this is ok
> > >
> > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> >
> > No, I think it is not.
>
> There are no GDSCs in IPQ9574. Can you suggest how to proceed.
You need to update the binding and either make the power domains
property optional in the binding or dependent on the SoC.
> > > + ssphy_0: phy@7d000 {
> >
> > Nit: usually the label usb_0_qmpphy
> >
> > > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > > + reg = <0x0007d000 0xa00>;
> > > + #phy-cells = <0>;
> > > +
> > > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > + <&xo_board_clk>,
> > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > + <&gcc GCC_USB0_PIPE_CLK>;
> > > + clock-names = "aux",
> > > + "ref",
> > > + "com_aux",
This is not the right name for this clock so you need to update the
binding first.
Please be more careful.
> > > + "pipe";
> > > +
> > > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > > + reset-names = "phy",
> > > + "phy_phy";
> > > +
> > > + vdda-pll-supply = <®_usb_1p8>;
> > > + vdda-phy-supply = <®_usb_0p925>;
> > > +
> > > + status = "disabled";
> > > +
> > > + #clock-cells = <0>;
> > > + clock-output-names = "usb0_pipe_clk";
> > > + };
Johan
On Fri, Mar 31, 2023 at 12:19:10PM +0200, Johan Hovold wrote:
> On Fri, Mar 31, 2023 at 02:57:11PM +0530, Varadarajan Narayanan wrote:
> > On Thu, Mar 30, 2023 at 12:44:40PM +0300, Dmitry Baryshkov wrote:
> > > On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> > > <quic_varada@quicinc.com> wrote:
> > > >
> > > > Add USB phy and controller related nodes
> > > >
> > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > ---
> > > > Changes in v5:
> > > > - Fix additional comments
> > > > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > > - 'make dtbs_check' giving the following messages since
> > > > ipq9574 doesn't have power domains. Hope this is ok
> > > >
> > > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> > > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> > > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > >
> > > No, I think it is not.
> >
> > There are no GDSCs in IPQ9574. Can you suggest how to proceed.
>
> You need to update the binding and either make the power domains
> property optional in the binding or dependent on the SoC.
>
> > > > + ssphy_0: phy@7d000 {
> > >
> > > Nit: usually the label usb_0_qmpphy
> > >
> > > > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > > > + reg = <0x0007d000 0xa00>;
> > > > + #phy-cells = <0>;
> > > > +
> > > > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > > + <&xo_board_clk>,
> > > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > > + <&gcc GCC_USB0_PIPE_CLK>;
> > > > + clock-names = "aux",
> > > > + "ref",
> > > > + "com_aux",
>
> This is not the right name for this clock so you need to update the
> binding first.
>
> Please be more careful.
Thanks for your feedback. Have posted v6 with the above corrections.
-Varada
>
> > > > + "pipe";
> > > > +
> > > > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > > > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > > > + reset-names = "phy",
> > > > + "phy_phy";
> > > > +
> > > > + vdda-pll-supply = <®_usb_1p8>;
> > > > + vdda-phy-supply = <®_usb_0p925>;
> > > > +
> > > > + status = "disabled";
> > > > +
> > > > + #clock-cells = <0>;
> > > > + clock-output-names = "usb0_pipe_clk";
> > > > + };
>
> Johan
On Wed, Apr 05, 2023 at 02:28:32PM +0530, Varadarajan Narayanan wrote:
> On Fri, Mar 31, 2023 at 12:19:10PM +0200, Johan Hovold wrote:
> > > > > + ssphy_0: phy@7d000 {
> > > >
> > > > Nit: usually the label usb_0_qmpphy
> > > >
> > > > > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > > > > + reg = <0x0007d000 0xa00>;
> > > > > + #phy-cells = <0>;
> > > > > +
> > > > > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > > > + <&xo_board_clk>,
> > > > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > > > + <&gcc GCC_USB0_PIPE_CLK>;
> > > > > + clock-names = "aux",
> > > > > + "ref",
> > > > > + "com_aux",
> >
> > This is not the right name for this clock so you need to update the
> > binding first.
> >
> > Please be more careful.
>
> Thanks for your feedback. Have posted v6 with the above corrections.
Thanks for the heads up. But for future submission, please try to
remember to add people that have provided feedback on CC when posting
new revisions.
Johan
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