arch/riscv/include/asm/vector.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
Fix [1] save/restore vector register error
Link: https://lore.kernel.org/all/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com/ [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/include/asm/vector.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index e8a83f55be2b..7df6355023a3 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
THEAD_VSETVLI_T4X0E8M8D1
THEAD_VSB_V_V0T0
"add t0, t0, t4\n\t"
- THEAD_VSB_V_V0T0
+ THEAD_VSB_V_V8T0
"add t0, t0, t4\n\t"
- THEAD_VSB_V_V0T0
+ THEAD_VSB_V_V16T0
"add t0, t0, t4\n\t"
- THEAD_VSB_V_V0T0
+ THEAD_VSB_V_V24T0
: : "r" (datap) : "memory", "t0", "t4");
} else {
asm volatile (
@@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
THEAD_VSETVLI_T4X0E8M8D1
THEAD_VLB_V_V0T0
"add t0, t0, t4\n\t"
- THEAD_VLB_V_V0T0
+ THEAD_VLB_V_V8T0
"add t0, t0, t4\n\t"
- THEAD_VLB_V_V0T0
+ THEAD_VLB_V_V16T0
"add t0, t0, t4\n\t"
- THEAD_VLB_V_V0T0
+ THEAD_VLB_V_V24T0
: : "r" (datap) : "memory", "t0", "t4");
} else {
asm volatile (
--
2.47.2
Hi Han,
On 5/22/25 19:27, Han Gao wrote:
> Fix [1] save/restore vector register error
>
> Link: https://lore.kernel.org/all/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com/ [1]
Would you mind rephrasing the log? It should explain what was wrong and
how you fixed it.
Thanks,
Alex
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> ---
> arch/riscv/include/asm/vector.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index e8a83f55be2b..7df6355023a3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
> THEAD_VSETVLI_T4X0E8M8D1
> THEAD_VSB_V_V0T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V8T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V16T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V24T0
> : : "r" (datap) : "memory", "t0", "t4");
> } else {
> asm volatile (
> @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
> THEAD_VSETVLI_T4X0E8M8D1
> THEAD_VLB_V_V0T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V8T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V16T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V24T0
> : : "r" (datap) : "memory", "t0", "t4");
> } else {
> asm volatile (
I will release v2 later to add explanation and add fix tag
Thanks,
Han
On Fri, May 23, 2025 at 4:54 PM Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> Hi Han,
>
> On 5/22/25 19:27, Han Gao wrote:
> > Fix [1] save/restore vector register error
> >
> > Link: https://lore.kernel.org/all/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com/ [1]
>
>
> Would you mind rephrasing the log? It should explain what was wrong and
> how you fixed it.
>
> Thanks,
>
> Alex
>
>
> >
> > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > ---
> > arch/riscv/include/asm/vector.h | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> > index e8a83f55be2b..7df6355023a3 100644
> > --- a/arch/riscv/include/asm/vector.h
> > +++ b/arch/riscv/include/asm/vector.h
> > @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
> > THEAD_VSETVLI_T4X0E8M8D1
> > THEAD_VSB_V_V0T0
> > "add t0, t0, t4\n\t"
> > - THEAD_VSB_V_V0T0
> > + THEAD_VSB_V_V8T0
> > "add t0, t0, t4\n\t"
> > - THEAD_VSB_V_V0T0
> > + THEAD_VSB_V_V16T0
> > "add t0, t0, t4\n\t"
> > - THEAD_VSB_V_V0T0
> > + THEAD_VSB_V_V24T0
> > : : "r" (datap) : "memory", "t0", "t4");
> > } else {
> > asm volatile (
> > @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
> > THEAD_VSETVLI_T4X0E8M8D1
> > THEAD_VLB_V_V0T0
> > "add t0, t0, t4\n\t"
> > - THEAD_VLB_V_V0T0
> > + THEAD_VLB_V_V8T0
> > "add t0, t0, t4\n\t"
> > - THEAD_VLB_V_V0T0
> > + THEAD_VLB_V_V16T0
> > "add t0, t0, t4\n\t"
> > - THEAD_VLB_V_V0T0
> > + THEAD_VLB_V_V24T0
> > : : "r" (datap) : "memory", "t0", "t4");
> > } else {
> > asm volatile (
On Fri, 23 May 2025 02:46:50 PDT (-0700), rabenda.cn@gmail.com wrote:
> I will release v2 later to add explanation and add fix tag
Sorry if I missed it, but I don't see a v2 (I'm scrubbing through stuff
post merge window).
>
> Thanks,
>
> Han
>
> On Fri, May 23, 2025 at 4:54 PM Alexandre Ghiti <alex@ghiti.fr> wrote:
>>
>> Hi Han,
>>
>> On 5/22/25 19:27, Han Gao wrote:
>> > Fix [1] save/restore vector register error
>> >
>> > Link: https://lore.kernel.org/all/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com/ [1]
>>
>>
>> Would you mind rephrasing the log? It should explain what was wrong and
>> how you fixed it.
>>
>> Thanks,
>>
>> Alex
>>
>>
>> >
>> > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
>> > ---
>> > arch/riscv/include/asm/vector.h | 12 ++++++------
>> > 1 file changed, 6 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
>> > index e8a83f55be2b..7df6355023a3 100644
>> > --- a/arch/riscv/include/asm/vector.h
>> > +++ b/arch/riscv/include/asm/vector.h
>> > @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
>> > THEAD_VSETVLI_T4X0E8M8D1
>> > THEAD_VSB_V_V0T0
>> > "add t0, t0, t4\n\t"
>> > - THEAD_VSB_V_V0T0
>> > + THEAD_VSB_V_V8T0
>> > "add t0, t0, t4\n\t"
>> > - THEAD_VSB_V_V0T0
>> > + THEAD_VSB_V_V16T0
>> > "add t0, t0, t4\n\t"
>> > - THEAD_VSB_V_V0T0
>> > + THEAD_VSB_V_V24T0
>> > : : "r" (datap) : "memory", "t0", "t4");
>> > } else {
>> > asm volatile (
>> > @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
>> > THEAD_VSETVLI_T4X0E8M8D1
>> > THEAD_VLB_V_V0T0
>> > "add t0, t0, t4\n\t"
>> > - THEAD_VLB_V_V0T0
>> > + THEAD_VLB_V_V8T0
>> > "add t0, t0, t4\n\t"
>> > - THEAD_VLB_V_V0T0
>> > + THEAD_VLB_V_V16T0
>> > "add t0, t0, t4\n\t"
>> > - THEAD_VLB_V_V0T0
>> > + THEAD_VLB_V_V24T0
>> > : : "r" (datap) : "memory", "t0", "t4");
>> > } else {
>> > asm volatile (
On Tue, Jun 10, 2025 at 03:05:58PM -0700, Palmer Dabbelt wrote:
> On Fri, 23 May 2025 02:46:50 PDT (-0700), rabenda.cn@gmail.com wrote:
> > I will release v2 later to add explanation and add fix tag
>
> Sorry if I missed it, but I don't see a v2 (I'm scrubbing through stuff post
> merge window).
v2 is here: https://lore.kernel.org/all/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com/
- Charlie
>
> >
> > Thanks,
> >
> > Han
> >
> > On Fri, May 23, 2025 at 4:54 PM Alexandre Ghiti <alex@ghiti.fr> wrote:
> > >
> > > Hi Han,
> > >
> > > On 5/22/25 19:27, Han Gao wrote:
> > > > Fix [1] save/restore vector register error
> > > >
> > > > Link: https://lore.kernel.org/all/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com/ [1]
> > >
> > >
> > > Would you mind rephrasing the log? It should explain what was wrong and
> > > how you fixed it.
> > >
> > > Thanks,
> > >
> > > Alex
> > >
> > >
> > > >
> > > > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > > > ---
> > > > arch/riscv/include/asm/vector.h | 12 ++++++------
> > > > 1 file changed, 6 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> > > > index e8a83f55be2b..7df6355023a3 100644
> > > > --- a/arch/riscv/include/asm/vector.h
> > > > +++ b/arch/riscv/include/asm/vector.h
> > > > @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
> > > > THEAD_VSETVLI_T4X0E8M8D1
> > > > THEAD_VSB_V_V0T0
> > > > "add t0, t0, t4\n\t"
> > > > - THEAD_VSB_V_V0T0
> > > > + THEAD_VSB_V_V8T0
> > > > "add t0, t0, t4\n\t"
> > > > - THEAD_VSB_V_V0T0
> > > > + THEAD_VSB_V_V16T0
> > > > "add t0, t0, t4\n\t"
> > > > - THEAD_VSB_V_V0T0
> > > > + THEAD_VSB_V_V24T0
> > > > : : "r" (datap) : "memory", "t0", "t4");
> > > > } else {
> > > > asm volatile (
> > > > @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
> > > > THEAD_VSETVLI_T4X0E8M8D1
> > > > THEAD_VLB_V_V0T0
> > > > "add t0, t0, t4\n\t"
> > > > - THEAD_VLB_V_V0T0
> > > > + THEAD_VLB_V_V8T0
> > > > "add t0, t0, t4\n\t"
> > > > - THEAD_VLB_V_V0T0
> > > > + THEAD_VLB_V_V16T0
> > > > "add t0, t0, t4\n\t"
> > > > - THEAD_VLB_V_V0T0
> > > > + THEAD_VLB_V_V24T0
> > > > : : "r" (datap) : "memory", "t0", "t4");
> > > > } else {
> > > > asm volatile (
On Fri, May 23, 2025 at 01:27:01AM +0800, Han Gao wrote:
> Fix [1] save/restore vector register error
>
> Link: https://lore.kernel.org/all/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com/ [1]
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Thank you!
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/vector.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index e8a83f55be2b..7df6355023a3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
> THEAD_VSETVLI_T4X0E8M8D1
> THEAD_VSB_V_V0T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V8T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V16T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V24T0
> : : "r" (datap) : "memory", "t0", "t4");
> } else {
> asm volatile (
> @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
> THEAD_VSETVLI_T4X0E8M8D1
> THEAD_VLB_V_V0T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V8T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V16T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V24T0
> : : "r" (datap) : "memory", "t0", "t4");
> } else {
> asm volatile (
> --
> 2.47.2
>
I tested this patch with llama.cpp while adding xtheadvector support. Surprisingly, this bug did not prevent the LLM from generating plausible output, though the model's responses became noticeably less coherent. Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
Sorry, forgot to add the fix tag
Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
On Fri, May 23, 2025 at 2:28 AM Xiongchuan Tan
<tanxiongchuan@isrc.iscas.ac.cn> wrote:
>
> I tested this patch with llama.cpp while adding xtheadvector support.
> Surprisingly, this bug did not prevent the LLM from generating plausible
> output, though the model's responses became noticeably less coherent.
>
> Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
>
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