drivers/net/dsa/lantiq/mxl-gsw1xx.c | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
Despite being documented as self-clearing, the RANEG bit sometimes
remains set, preventing auto-negotiation from happening.
Manually clear the RANEG bit after 10ms as advised by MaxLinear.
In order to not hold RTNL during the 10ms of waiting schedule
delayed work to take care of clearing the bit asynchronously, which
is similar to the self-clearing behavior.
Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
Reported-by: Rasmus Villemoes <ravi@prevas.dk>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v2:
* cancel pending work before setting RANEG bit
* cancel pending work on remove and shutdown
* document that GSW1XX_RST_REQ_SGMII_SHELL also clears RANEG bit
* improve commit message
drivers/net/dsa/lantiq/mxl-gsw1xx.c | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/mxl-gsw1xx.c
index cf33a16fd183b..5232737778835 100644
--- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c
+++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c
@@ -11,10 +11,12 @@
#include <linux/bits.h>
#include <linux/delay.h>
+#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/regmap.h>
+#include <linux/workqueue.h>
#include <net/dsa.h>
#include "lantiq_gswip.h"
@@ -29,6 +31,7 @@ struct gsw1xx_priv {
struct regmap *clk;
struct regmap *shell;
struct phylink_pcs pcs;
+ struct delayed_work clear_raneg;
phy_interface_t tbi_interface;
struct gswip_priv gswip;
};
@@ -145,6 +148,8 @@ static void gsw1xx_pcs_disable(struct phylink_pcs *pcs)
{
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
+ cancel_delayed_work_sync(&priv->clear_raneg);
+
- /* Assert SGMII shell reset */
+ /* Assert SGMII shell reset (will also clear RANEG bit) */
regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
GSW1XX_RST_REQ_SGMII_SHELL);
@@ -428,12 +433,29 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
return 0;
}
+static void gsw1xx_pcs_clear_raneg(struct work_struct *work)
+{
+ struct gsw1xx_priv *priv =
+ container_of(work, struct gsw1xx_priv, clear_raneg.work);
+
+ regmap_clear_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
+ GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
+}
+
static void gsw1xx_pcs_an_restart(struct phylink_pcs *pcs)
{
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
+ cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
+
regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
+
+ /* despite being documented as self-clearing, the RANEG bit
+ * sometimes remains set, preventing auto-negotiation from happening.
+ * MaxLinear advises to manually clear the bit after 10ms.
+ */
+ schedule_delayed_work(&priv->clear_raneg, msecs_to_jiffies(10));
}
static void gsw1xx_pcs_link_up(struct phylink_pcs *pcs,
@@ -636,6 +658,8 @@ static int gsw1xx_probe(struct mdio_device *mdiodev)
if (ret)
return ret;
+ INIT_DELAYED_WORK(&priv->clear_raneg, gsw1xx_pcs_clear_raneg);
+
ret = gswip_probe_common(&priv->gswip, version);
if (ret)
return ret;
@@ -648,10 +672,14 @@ static int gsw1xx_probe(struct mdio_device *mdiodev)
static void gsw1xx_remove(struct mdio_device *mdiodev)
{
struct gswip_priv *priv = dev_get_drvdata(&mdiodev->dev);
+ struct gsw1xx_priv *gsw1xx_priv;
if (!priv)
return;
+ gsw1xx_priv = container_of(priv, struct gsw1xx_priv, gswip);
+ cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
+
gswip_disable_switch(priv);
dsa_unregister_switch(priv->ds);
@@ -660,10 +688,14 @@ static void gsw1xx_remove(struct mdio_device *mdiodev)
static void gsw1xx_shutdown(struct mdio_device *mdiodev)
{
struct gswip_priv *priv = dev_get_drvdata(&mdiodev->dev);
+ struct gsw1xx_priv *gsw1xx_priv;
if (!priv)
return;
+ gsw1xx_priv = container_of(priv, struct gsw1xx_priv, gswip);
+ cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
+
dev_set_drvdata(&mdiodev->dev, NULL);
gswip_disable_switch(priv);
--
2.52.0Hi Daniel,
kernel test robot noticed the following build errors:
[auto build test ERROR on net/main]
url: https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/net-dsa-mxl-gsw1xx-manually-clear-RANEG-bit/20251207-063852
base: net/main
patch link: https://lore.kernel.org/r/a90b206e9fd8e4248fd639afd5ae296454ac99b9.1765060046.git.daniel%40makrotopia.org
patch subject: [PATCH net v2] net: dsa: mxl-gsw1xx: manually clear RANEG bit
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20251208/202512080800.2VZCNFnY-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251208/202512080800.2VZCNFnY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512080800.2VZCNFnY-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/net/dsa/lantiq/mxl-gsw1xx.c:449:28: error: use of undeclared identifier 'gsw1xx_priv'
cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
^
1 error generated.
vim +/gsw1xx_priv +449 drivers/net/dsa/lantiq/mxl-gsw1xx.c
444
445 static void gsw1xx_pcs_an_restart(struct phylink_pcs *pcs)
446 {
447 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
448
> 449 cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
450
451 regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
452 GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
453
454 /* despite being documented as self-clearing, the RANEG bit
455 * sometimes remains set, preventing auto-negotiation from happening.
456 * MaxLinear advises to manually clear the bit after 10ms.
457 */
458 schedule_delayed_work(&priv->clear_raneg, msecs_to_jiffies(10));
459 }
460
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Daniel,
kernel test robot noticed the following build errors:
[auto build test ERROR on net/main]
url: https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/net-dsa-mxl-gsw1xx-manually-clear-RANEG-bit/20251207-063852
base: net/main
patch link: https://lore.kernel.org/r/a90b206e9fd8e4248fd639afd5ae296454ac99b9.1765060046.git.daniel%40makrotopia.org
patch subject: [PATCH net v2] net: dsa: mxl-gsw1xx: manually clear RANEG bit
config: um-allyesconfig (https://download.01.org/0day-ci/archive/20251208/202512080341.Vpa2e40b-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251208/202512080341.Vpa2e40b-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512080341.Vpa2e40b-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/net/dsa/lantiq/mxl-gsw1xx.c: In function 'gsw1xx_pcs_an_restart':
>> drivers/net/dsa/lantiq/mxl-gsw1xx.c:449:35: error: 'gsw1xx_priv' undeclared (first use in this function)
449 | cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
| ^~~~~~~~~~~
drivers/net/dsa/lantiq/mxl-gsw1xx.c:449:35: note: each undeclared identifier is reported only once for each function it appears in
vim +/gsw1xx_priv +449 drivers/net/dsa/lantiq/mxl-gsw1xx.c
444
445 static void gsw1xx_pcs_an_restart(struct phylink_pcs *pcs)
446 {
447 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
448
> 449 cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
450
451 regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
452 GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
453
454 /* despite being documented as self-clearing, the RANEG bit
455 * sometimes remains set, preventing auto-negotiation from happening.
456 * MaxLinear advises to manually clear the bit after 10ms.
457 */
458 schedule_delayed_work(&priv->clear_raneg, msecs_to_jiffies(10));
459 }
460
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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