RE: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825

Nitka, Grzegorz posted 8 patches 2 days, 12 hours ago
Only 0 patches received!
There is a newer version of this series
RE: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Posted by Nitka, Grzegorz 2 days, 12 hours ago
> -----Original Message-----
> From: Jakub Kicinski <kuba@kernel.org>
> Sent: Friday, June 5, 2026 12:54 AM
> To: Nitka, Grzegorz <grzegorz.nitka@intel.com>
> Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; Oros, Petr <poros@redhat.com>;
> richardcochran@gmail.com; andrew+netdev@lunn.ch; Kitszel, Przemyslaw
> <przemyslaw.kitszel@intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>; Prathosh.Satish@microchip.com; Vecera,
> Ivan <ivecera@redhat.com>; jiri@resnulli.us; Kubalewski, Arkadiusz
> <arkadiusz.kubalewski@intel.com>; vadim.fedorenko@linux.dev;
> donald.hunter@gmail.com; horms@kernel.org; pabeni@redhat.com;
> davem@davemloft.net; edumazet@google.com
> Subject: Re: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full
> TX reference clock control for E825
> 
> On Thu, 4 Jun 2026 20:05:54 +0000 Nitka, Grzegorz wrote:
> > > On Fri, 29 May 2026 16:26:20 +0200 Grzegorz Nitka wrote:
> > > > NOTE: This series is intentionally submitted on net-next (not
> > > > intel-wired-lan) as early feedback of DPLL subsystem changes is
> > > > welcomed. In the past possible approaches were discussed in [1].
> > >
> > > I dug into 3 of the issues reported by Claude here and I think all
> > > are really preexisting. But I don't see why we wouldn't fix those
> > > first, and have a clean AI scan. Please send the fixes ASAP if you
> > > have them, if they are trivial they may make it for tomorrow's PR.
> >
> > Thanks for your feedback.
> > I'm not sure if I can identify exact 3 issues you mentioned above.
> > I see couple pre-existing issues reported in
> > https://sashiko.dev/#/patchset/20260529142628.1678955-1-
> grzegorz.nitka%40intel.com
> >   - 3 issues reported in [PATCH v12 net-next 3/8] dpll: extend pin notifier
> with notification source ID
> >   - 2 issues reported in [PATCH v12 net-next 5/8] ice: introduce TXC DPLL
> device and TX ref clock pin framework for E825
> >     The first one is false positive in my opinion.
> >
> > Did you mean those from patch 3/8?
> > It should be rather simple ones. Shall I submit it as a part of this series?
> > Or a new patch/patchset? (against next or net?)
> 
> Ugh, I think I missed that the caller looks at the ICE_FLAG_DPLL flag.
> So most of the deinit bugs are not actually bugs.
> 
> You can add the fixes to this series.

Hi Kuba. Just submitted v13.

It includes the following fixes for pre-existing issues:
  - dpll core fixes. Each AI review concern (3) is addressed in separate
    commit. If you think it's better to squash them, let me know (however
    it addresses issues from two different 'old' commits).
    Also, the hint form AI  to use different dpll xa_array (parent not pin) to
    address one of the issues, it simply does not work (WARNING flood observed,
    more details in patch 3/11)
  - ice driver fix for potential hung on flush_workqueue in error path for FW node pins

As you noted, two other pre-existing issues are covered by ICE_FLAG_DPLL.
I left the code as it is for those concerns.
There is one more pre-existing one, related to ice_ptp_link_change. As the fix seems to be
rather simple one, I believe I need more time for more comprehensive testing.
So my preference is to go with standard fix-path on 'net'.

Regards

Grzegorz
Re: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Posted by Jakub Kicinski 2 days, 5 hours ago
On Fri, 5 Jun 2026 16:10:19 +0000 Nitka, Grzegorz wrote:
> Hi Kuba. Just submitted v13.
> 
> It includes the following fixes for pre-existing issues:
>   - dpll core fixes. Each AI review concern (3) is addressed in separate
>     commit. If you think it's better to squash them, let me know (however
>     it addresses issues from two different 'old' commits).
>     Also, the hint form AI  to use different dpll xa_array (parent not pin) to
>     address one of the issues, it simply does not work (WARNING flood observed,
>     more details in patch 3/11)
>   - ice driver fix for potential hung on flush_workqueue in error path for FW node pins
> 
> As you noted, two other pre-existing issues are covered by ICE_FLAG_DPLL.
> I left the code as it is for those concerns.
> There is one more pre-existing one, related to ice_ptp_link_change. As the fix seems to be
> rather simple one, I believe I need more time for more comprehensive testing.
> So my preference is to go with standard fix-path on 'net'.

SG, thanks!

BTW either you or Arkadiusz should chime in on the NCO thread, please:
https://lore.kernel.org/all/20260531194423.383366-2-ivecera@redhat.com/
Shouldn't take much time to express an opinion, I hope.
RE: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Posted by Nitka, Grzegorz 9 hours ago

> -----Original Message-----
> From: Jakub Kicinski <kuba@kernel.org>
> Sent: Saturday, June 6, 2026 1:26 AM
> To: Nitka, Grzegorz <grzegorz.nitka@intel.com>
> Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; Oros, Petr <poros@redhat.com>;
> richardcochran@gmail.com; andrew+netdev@lunn.ch; Kitszel, Przemyslaw
> <przemyslaw.kitszel@intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>; Prathosh.Satish@microchip.com; Vecera,
> Ivan <ivecera@redhat.com>; jiri@resnulli.us; Kubalewski, Arkadiusz
> <arkadiusz.kubalewski@intel.com>; vadim.fedorenko@linux.dev;
> donald.hunter@gmail.com; horms@kernel.org; pabeni@redhat.com;
> davem@davemloft.net; edumazet@google.com
> Subject: Re: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full
> TX reference clock control for E825
> 
> On Fri, 5 Jun 2026 16:10:19 +0000 Nitka, Grzegorz wrote:
> > Hi Kuba. Just submitted v13.
> >
> > It includes the following fixes for pre-existing issues:
> >   - dpll core fixes. Each AI review concern (3) is addressed in separate
> >     commit. If you think it's better to squash them, let me know (however
> >     it addresses issues from two different 'old' commits).
> >     Also, the hint form AI  to use different dpll xa_array (parent not pin) to
> >     address one of the issues, it simply does not work (WARNING flood
> observed,
> >     more details in patch 3/11)
> >   - ice driver fix for potential hung on flush_workqueue in error path for FW
> node pins
> >
> > As you noted, two other pre-existing issues are covered by ICE_FLAG_DPLL.
> > I left the code as it is for those concerns.
> > There is one more pre-existing one, related to ice_ptp_link_change. As the fix
> seems to be
> > rather simple one, I believe I need more time for more comprehensive
> testing.
> > So my preference is to go with standard fix-path on 'net'.
> 
> SG, thanks!
> 
> BTW either you or Arkadiusz should chime in on the NCO thread, please:
> https://lore.kernel.org/all/20260531194423.383366-2-
> ivecera@redhat.com/
> Shouldn't take much time to express an opinion, I hope.

Sure, we will do on Monday (we had a long weekend this week, so limited
capacity).

Regarding this series. There are another pre-existing dpll-core findings
reported in v13. As I still had to address valid critical/high issues in 'ice',
I added 2 simple dpll-core fixes in v14 (just submitted, along with ice 
improvements).

Regards

Grzegorz