> -----Original Message-----
> From: Loktionov, Aleksandr <aleksandr.loktionov@intel.com>
> Sent: Friday, May 15, 2026 2:14 PM
> To: Nitka, Grzegorz <grzegorz.nitka@intel.com>; netdev@vger.kernel.org
> Cc: Vecera, Ivan <ivecera@redhat.com>; vadim.fedorenko@linux.dev;
> kuba@kernel.org; jiri@resnulli.us; edumazet@google.com; Kitszel,
> Przemyslaw <przemyslaw.kitszel@intel.com>; richardcochran@gmail.com;
> donald.hunter@gmail.com; linux-kernel@vger.kernel.org; Kubalewski,
> Arkadiusz <arkadiusz.kubalewski@intel.com>; andrew+netdev@lunn.ch;
> intel-wired-lan@lists.osuosl.org; horms@kernel.org;
> Prathosh.Satish@microchip.com; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>; pabeni@redhat.com; davem@davemloft.net
> Subject: RE: [Intel-wired-lan] [PATCH v9 net-next 0/8] dpll/ice: Add generic
> DPLL type and full TX reference clock control for E825
> 
> 
> 
> > -----Original Message-----
> > From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf
> > Of Grzegorz Nitka
> > Sent: Friday, May 15, 2026 1:00 AM
> > To: netdev@vger.kernel.org
> > Cc: Vecera, Ivan <ivecera@redhat.com>; vadim.fedorenko@linux.dev;
> > kuba@kernel.org; jiri@resnulli.us; edumazet@google.com; Kitszel,
> > Przemyslaw <przemyslaw.kitszel@intel.com>; richardcochran@gmail.com;
> > donald.hunter@gmail.com; linux-kernel@vger.kernel.org; Kubalewski,
> > Arkadiusz <arkadiusz.kubalewski@intel.com>; andrew+netdev@lunn.ch;
> > intel-wired-lan@lists.osuosl.org; horms@kernel.org;
> > Prathosh.Satish@microchip.com; Nguyen, Anthony L
> > <anthony.l.nguyen@intel.com>; pabeni@redhat.com;
> davem@davemloft.net
> > Subject: [Intel-wired-lan] [PATCH v9 net-next 0/8] dpll/ice: Add
> > generic DPLL type and full TX reference clock control for E825
> >
> > NOTE: This series is intentionally submitted on net-next (not
> > intel-wired-lan) as early feedback of DPLL subsystem changes is
> > welcomed. In the past possible approaches were discussed in [1].
> >
> > This series adds TX reference clock support for E825 devices and
> > exposes TX clock selection and synchronization status via the Linux
> > DPLL subsystem.
> >
> > Here is the high-level connection diagram for E825 device:
> 
> ...
> 
> > ice_dpll_deinit_txclk_pins and
> >   ice_dpll_pin_notify_work() that is about to register the SYNCE pin
> >   (patch 5/8)
> > - resolved potential path deadlock during driver probe and error
> > path
> >   (patch 5/8)
> > - relaxed kernel-doc regarding cpi mutex usage (patch 6/8)
> > - fixed ice_cpi.c header (patch 6/8)
> > - fix retry mechanism in ice_cpi_wait_req0_ack0 (patch 6/8)
> > - fix potrntial leaving LM.REQ stuck asserted on the hardware (patch
> > 6/8)
> > - fix kernel-doc for ice_cpi_ena_dis_clk_ref
> > - removed unused CPI definitions (patch 6/8)
> > - fix header inclusion (patch 6/8)
> > - addressed Sashiko issues for patch (8/8)
> >
> > Changes in v7:
> > - rebased
> > - replace TXC-specific DPLL type with DPLL_TYPE_GENERIC (patch 1/8)
> > - update TXC framework to use DPLL_TYPE_GENERIC instead of
> > DPLL_TYPE_GENERIC
> DPLL_TYPE_GENERIC instead of DPLL_TYPE_GENERIC
> Something is wrong
> 

Correct! Typo ...  the correct statement should be:
DPLL_TYPE_GENERIC instead of DPLL_TYPE_TXC

Thanks

Grzegorz
> ...
> 
> > --
> > 2.39.3