The patch series fixes dt-schema validation errors that can be reproduced
using the following: make ARCH=riscv defconfig; make ARCH=riscv
dt_binding_check dtbs_check


Atul Khare (4):
  dt-bindings: sifive: Support 1024 hart contexts
  dt-bindings: sifive: add cache-set value of 2048
  dt-bindings: sifive: delete 'clock' / 'status'
  dt-bindings: sifive: add gpio-line-names

 Documentation/devicetree/bindings/gpio/sifive,gpio.yaml      | 3 +++
 Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 +++-
 Documentation/devicetree/bindings/timer/sifive,clint.yaml    | 2 ++
 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts  | 4 ----
 4 files changed, 8 insertions(+), 5 deletions(-)

--
2.35.1

On 21/04/2022 06:07, Atul Khare wrote:
> The patch series fixes dt-schema validation errors that can be reproduced
> using the following: make ARCH=riscv defconfig; make ARCH=riscv
> dt_binding_check dtbs_check

Hey Atul,
I assume you never sent a v2 of these patches?
Could you rebase & resend them with a more complete CC list please?
I think you can drop the microchip dts patch, I didn't see this
series and dropped the clock property myself.

Was trying to clear the errors myself & recalled that Palmer said
you were working on them. Wondered what had happened but this makes
a lot of sense.

Could you also thread the series so that b4 picks it up properly?
Thanks,
Conor.

> 
> 
> Atul Khare (4):
>   dt-bindings: sifive: Support 1024 hart contexts
>   dt-bindings: sifive: add cache-set value of 2048
>   dt-bindings: sifive: delete 'clock' / 'status'
>   dt-bindings: sifive: add gpio-line-names
> 
>  Documentation/devicetree/bindings/gpio/sifive,gpio.yaml      | 3 +++
>  Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 +++-
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml    | 2 ++
>  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts  | 4 ----
>  4 files changed, 8 insertions(+), 5 deletions(-)
> 
> --
> 2.35.1