> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Tuesday, June 6, 2023 10:18 PM
> 
> > > > It's not necessarily to add reserved regions to the IOAS of the parent
> > > > hwpt since the device doesn't access that address space after it's
> > > > attached to stage-1. The parent is used only for address translation
> > > > in the iommu side.
> > >
> > > But if we don't put them in the IOAS of the parent there is no way for
> > > userspace to learn what they are to forward to the VM ?
> >
> > emmm I wonder whether that is the right interface to report
> > per-device reserved regions.
> 
> The iommu driver needs to report different reserved regions for the S1
> and S2 iommu_domains, 

I can see the difference between RID and RID+PASID, but not sure whether
it's a actual requirement regarding to attached domain.

e.g. if only talking about RID then the same set of reserved regions should
be reported for both S1 attach and S2 attach.

> and the IOAS should only get the reserved regions for the S2.
> 
> Currently the API has no way to report per-domain reserved regions and
> that is possibly OK for now. The S2 really doesn't have reserved
> regions beyond the domain aperture.
> 
> So an ioctl to directly query the reserved regions for a dev_id makes
> sense.

Or more specifically query the reserved regions for RID-based access.

Ideally for PASID there is no reserved region otherwise SVA won't work. 😊

> 
> > > Since we expect the parent IOAS to be usable in an identity mode I
> > > think they should be added, at least I can't see a reason not to add
> > > them.
> >
> > this is a good point.
> 
> But it mixes things
> 
> The S2 doesn't have reserved ranges restrictions, we always have some
> model of a S1, even for identity mode, that would carry the reserved
> ranges.
> 
> > With that it makes more sense to make it a vendor specific choice.
> 
> It isn't vendor specific, the ranges come from the domain that is
> attached to the IOAS, and we simply don't import ranges for a S2
> domain.
> 

With above I think the ranges are static per device.

When talking about RID-based nesting alone, ARM needs to add reserved
regions to the parent IOAS as identity is a valid S1 mode in nesting.

But for Intel RID nesting excludes identity (which becomes a direct
attach to S2) so the reserved regions apply to S1 instead of the parent IOAS.

On Fri, Jun 16, 2023 at 02:43:13AM +0000, Tian, Kevin wrote:
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > Sent: Tuesday, June 6, 2023 10:18 PM
> > 
> > > > > It's not necessarily to add reserved regions to the IOAS of the parent
> > > > > hwpt since the device doesn't access that address space after it's
> > > > > attached to stage-1. The parent is used only for address translation
> > > > > in the iommu side.
> > > >
> > > > But if we don't put them in the IOAS of the parent there is no way for
> > > > userspace to learn what they are to forward to the VM ?
> > >
> > > emmm I wonder whether that is the right interface to report
> > > per-device reserved regions.
> > 
> > The iommu driver needs to report different reserved regions for the S1
> > and S2 iommu_domains, 
> 
> I can see the difference between RID and RID+PASID, but not sure whether
> it's a actual requirement regarding to attached domain.

No, it isn't RID or RID+PASID here

The S2 has a different set of reserved regsions than the S1 because
the S2's IOVA does not appear on the bus.

So the S2's reserved regions are entirely an artifact of how the IOMMU
HW itself works when nesting.

We can probably get by with some documented slightly messy rules that
the reserved_regions only applies to directly RID attached domains. S2
and PASID attachments always have no reserved spaces.

> When talking about RID-based nesting alone, ARM needs to add reserved
> regions to the parent IOAS as identity is a valid S1 mode in nesting.

No, definately not. The S2 has no reserved regions because it is an
internal IOVA, and we should not abuse that.

Reflecting the requirements for an identity map is something all iommu
HW needs to handle, we should figure out how to do that properly.

> But for Intel RID nesting excludes identity (which becomes a direct
> attach to S2) so the reserved regions apply to S1 instead of the parent IOAS.

IIRC all the HW models will assign their S2's as a RID attached "S1"
during boot time to emulate "no translation"?

They all need to learn what the allowed identiy mapping is so that the
VMM can construct a compatible guest address space, independently of
any IOAS restrictions.

Jason

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Monday, June 19, 2023 8:37 PM
> 
> On Fri, Jun 16, 2023 at 02:43:13AM +0000, Tian, Kevin wrote:
> > > From: Jason Gunthorpe <jgg@nvidia.com>
> > > Sent: Tuesday, June 6, 2023 10:18 PM
> > >
> > > > > > It's not necessarily to add reserved regions to the IOAS of the parent
> > > > > > hwpt since the device doesn't access that address space after it's
> > > > > > attached to stage-1. The parent is used only for address translation
> > > > > > in the iommu side.
> > > > >
> > > > > But if we don't put them in the IOAS of the parent there is no way for
> > > > > userspace to learn what they are to forward to the VM ?
> > > >
> > > > emmm I wonder whether that is the right interface to report
> > > > per-device reserved regions.
> > >
> > > The iommu driver needs to report different reserved regions for the S1
> > > and S2 iommu_domains,
> >
> > I can see the difference between RID and RID+PASID, but not sure whether
> > it's a actual requirement regarding to attached domain.
> 
> No, it isn't RID or RID+PASID here
> 
> The S2 has a different set of reserved regsions than the S1 because
> the S2's IOVA does not appear on the bus.
> 
> So the S2's reserved regions are entirely an artifact of how the IOMMU
> HW itself works when nesting.
> 
> We can probably get by with some documented slightly messy rules that
> the reserved_regions only applies to directly RID attached domains. S2
> and PASID attachments always have no reserved spaces.
> 
> > When talking about RID-based nesting alone, ARM needs to add reserved
> > regions to the parent IOAS as identity is a valid S1 mode in nesting.
> 
> No, definately not. The S2 has no reserved regions because it is an
> internal IOVA, and we should not abuse that.
> 
> Reflecting the requirements for an identity map is something all iommu
> HW needs to handle, we should figure out how to do that properly.

I wonder whether we have argued passed each other.

This series adds reserved regions to S2. I challenged the necessity as
S2 is not directly accessed by the device.

Then you replied that doing so still made sense to support identity S1.

But now looks you also agree that reserved regions should not be 
added to S2 except supporting identity S1 needs more thought?

> 
> > But for Intel RID nesting excludes identity (which becomes a direct
> > attach to S2) so the reserved regions apply to S1 instead of the parent IOAS.
> 
> IIRC all the HW models will assign their S2's as a RID attached "S1"
> during boot time to emulate "no translation"?

I'm not sure what it means...

> 
> They all need to learn what the allowed identiy mapping is so that the
> VMM can construct a compatible guest address space, independently of
> any IOAS restrictions.
> 

Intel VT-d supports 4 configurations:
  - passthrough (i.e. identity mapped)
  - S1 only
  - S2 only
  - nested

'S2 only' is used when vIOMMU is configured in passthrough.

'nested' is used when vIOMMU is configured in 'S1 only'.

So in any case 'identity' is not a business of nesting in the VT-d context.

My understanding of ARM SMMU is that from host p.o.v. the CD is the
S1 in the nested configuration. 'identity' is one configuration in the CD
then it's in the business of nesting.

My preference was that ALLOC_HWPT allows vIOMMU to opt whether
reserved regions of dev_id should be added to the IOAS of the parent
S2 hwpt.

On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
> I wonder whether we have argued passed each other.
> 
> This series adds reserved regions to S2. I challenged the necessity as
> S2 is not directly accessed by the device.
> 
> Then you replied that doing so still made sense to support identity
> S1.

I think I said/ment if we attach the "s2" iommu domain as a direct
attach for identity - eg at boot time, then the IOAS must gain the
reserved regions. This is our normal protocol.

But when we use the "s2" iommu domain as an actual nested S2 then we
don't gain reserved regions.

> Intel VT-d supports 4 configurations:
>   - passthrough (i.e. identity mapped)
>   - S1 only
>   - S2 only
>   - nested
> 
> 'S2 only' is used when vIOMMU is configured in passthrough.

S2 only is modeled as attaching an S2 format iommu domain to the RID,
and when this is done the IOAS should gain the reserved regions
because it is no different behavior than attaching any other iommu
domain to a RID.

When the S2 is replaced with a S1 nest then the IOAS should loose
those reserved regions since it is no longer attached to a RID.

> My understanding of ARM SMMU is that from host p.o.v. the CD is the
> S1 in the nested configuration. 'identity' is one configuration in the CD
> then it's in the business of nesting.

I think it is the same. A CD doesn't come into the picture until the
guest installs a CD pointing STE. Until that time the S2 is being used
as identity.

It sounds like the same basic flow.

> My preference was that ALLOC_HWPT allows vIOMMU to opt whether
> reserved regions of dev_id should be added to the IOAS of the parent
> S2 hwpt.

Having an API to explicitly load reserved regions of a specific device
to an IOAS makes some sense to me.

Jason

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Tuesday, June 20, 2023 8:47 PM
> 
> On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
> > I wonder whether we have argued passed each other.
> >
> > This series adds reserved regions to S2. I challenged the necessity as
> > S2 is not directly accessed by the device.
> >
> > Then you replied that doing so still made sense to support identity
> > S1.
> 
> I think I said/ment if we attach the "s2" iommu domain as a direct
> attach for identity - eg at boot time, then the IOAS must gain the
> reserved regions. This is our normal protocol.
> 
> But when we use the "s2" iommu domain as an actual nested S2 then we
> don't gain reserved regions.

Then we're aligned.

Yi/Nicolin, please update this series to not automatically add reserved
regions to S2 in the nesting configuration.

It also implies that the user cannot rely on IOAS_IOVA_RANGES to
learn reserved regions for arranging addresses in S1.

Then we also need a new ioctl to report reserved regions per dev_id.

> 
> > Intel VT-d supports 4 configurations:
> >   - passthrough (i.e. identity mapped)
> >   - S1 only
> >   - S2 only
> >   - nested
> >
> > 'S2 only' is used when vIOMMU is configured in passthrough.
> 
> S2 only is modeled as attaching an S2 format iommu domain to the RID,
> and when this is done the IOAS should gain the reserved regions
> because it is no different behavior than attaching any other iommu
> domain to a RID.
> 
> When the S2 is replaced with a S1 nest then the IOAS should loose
> those reserved regions since it is no longer attached to a RID.

yes

> 
> > My understanding of ARM SMMU is that from host p.o.v. the CD is the
> > S1 in the nested configuration. 'identity' is one configuration in the CD
> > then it's in the business of nesting.
> 
> I think it is the same. A CD doesn't come into the picture until the
> guest installs a CD pointing STE. Until that time the S2 is being used
> as identity.
> 
> It sounds like the same basic flow.

After a CD table is installed in a STE I assume the SMMU still allows to
configure an individual CD entry as identity? e.g. while vSVA is enabled
on a device the guest can continue to keep CD#0 as identity when the
default domain of the device is set as 'passthrough'. In this case the
IOAS still needs to gain reserved regions even though S2 is not directly
attached from host p.o.v.

> 
> > My preference was that ALLOC_HWPT allows vIOMMU to opt whether
> > reserved regions of dev_id should be added to the IOAS of the parent
> > S2 hwpt.
> 
> Having an API to explicitly load reserved regions of a specific device
> to an IOAS makes some sense to me.
> 
> Jason

On Wed, Jun 21, 2023 at 06:02:21AM +0000, Tian, Kevin wrote:

> > On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
> > > I wonder whether we have argued passed each other.
> > >
> > > This series adds reserved regions to S2. I challenged the necessity as
> > > S2 is not directly accessed by the device.
> > >
> > > Then you replied that doing so still made sense to support identity
> > > S1.
> >
> > I think I said/ment if we attach the "s2" iommu domain as a direct
> > attach for identity - eg at boot time, then the IOAS must gain the
> > reserved regions. This is our normal protocol.
> >
> > But when we use the "s2" iommu domain as an actual nested S2 then we
> > don't gain reserved regions.
> 
> Then we're aligned.
> 
> Yi/Nicolin, please update this series to not automatically add reserved
> regions to S2 in the nesting configuration.

I'm a bit late for the conversation here. Yet, how about the
IOMMU_RESV_SW_MSI on ARM in the nesting configuration? We'd
still call iommufd_group_setup_msi() on the S2 HWPT, despite
attaching the device to a nested S1 HWPT right?

> It also implies that the user cannot rely on IOAS_IOVA_RANGES to
> learn reserved regions for arranging addresses in S1.
> 
> Then we also need a new ioctl to report reserved regions per dev_id.

So, in a nesting configuration, QEMU would poll a device's S2
MSI region (i.e. IOMMU_RESV_SW_MSI) to prevent conflict?

Thanks
Nic

> From: Nicolin Chen <nicolinc@nvidia.com>
> Sent: Thursday, June 22, 2023 1:13 AM
> 
> On Wed, Jun 21, 2023 at 06:02:21AM +0000, Tian, Kevin wrote:
> 
> > > On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
> > > > I wonder whether we have argued passed each other.
> > > >
> > > > This series adds reserved regions to S2. I challenged the necessity as
> > > > S2 is not directly accessed by the device.
> > > >
> > > > Then you replied that doing so still made sense to support identity
> > > > S1.
> > >
> > > I think I said/ment if we attach the "s2" iommu domain as a direct
> > > attach for identity - eg at boot time, then the IOAS must gain the
> > > reserved regions. This is our normal protocol.
> > >
> > > But when we use the "s2" iommu domain as an actual nested S2 then we
> > > don't gain reserved regions.
> >
> > Then we're aligned.
> >
> > Yi/Nicolin, please update this series to not automatically add reserved
> > regions to S2 in the nesting configuration.
> 
> I'm a bit late for the conversation here. Yet, how about the
> IOMMU_RESV_SW_MSI on ARM in the nesting configuration? We'd
> still call iommufd_group_setup_msi() on the S2 HWPT, despite
> attaching the device to a nested S1 HWPT right?

Yes, based on current design of ARM nesting.

But please special case it instead of pretending that all reserved regions
are added to IOAS which is wrong in concept based on the discussion.

> 
> > It also implies that the user cannot rely on IOAS_IOVA_RANGES to
> > learn reserved regions for arranging addresses in S1.
> >
> > Then we also need a new ioctl to report reserved regions per dev_id.
> 
> So, in a nesting configuration, QEMU would poll a device's S2
> MSI region (i.e. IOMMU_RESV_SW_MSI) to prevent conflict?
> 

Qemu needs to know all the reserved regions of the device and skip
them when arranging S1 layout.

I'm not sure whether the MSI region needs a special MSI type or
just a general RESV_DIRECT type for 1:1 mapping, though.

On Mon, Jun 26, 2023 at 06:42:58AM +0000, Tian, Kevin wrote:

> > > Yi/Nicolin, please update this series to not automatically add reserved
> > > regions to S2 in the nesting configuration.
> >
> > I'm a bit late for the conversation here. Yet, how about the
> > IOMMU_RESV_SW_MSI on ARM in the nesting configuration? We'd
> > still call iommufd_group_setup_msi() on the S2 HWPT, despite
> > attaching the device to a nested S1 HWPT right?
> 
> Yes, based on current design of ARM nesting.
> 
> But please special case it instead of pretending that all reserved regions
> are added to IOAS which is wrong in concept based on the discussion.

Ack. Yi made a version of change dropping it completely along
with the iommufd_group_setup_msi() call for a nested S1 HWPT.
So I thought there was a misalignment. I made another version
preserving the pathway for MSI on ARM, and perhaps we should
go with this one:
https://github.com/nicolinc/iommufd/commit/c63829a12d35f2d7a390f42821a079f8a294cff8

> > > It also implies that the user cannot rely on IOAS_IOVA_RANGES to
> > > learn reserved regions for arranging addresses in S1.
> > >
> > > Then we also need a new ioctl to report reserved regions per dev_id.
> >
> > So, in a nesting configuration, QEMU would poll a device's S2
> > MSI region (i.e. IOMMU_RESV_SW_MSI) to prevent conflict?
> >
> 
> Qemu needs to know all the reserved regions of the device and skip
> them when arranging S1 layout.

OK.

> I'm not sure whether the MSI region needs a special MSI type or
> just a general RESV_DIRECT type for 1:1 mapping, though.

I don't quite get this part. Isn't MSI having IOMMU_RESV_MSI
and IOMMU_RESV_SW_MSI? Or does it juset mean we should report
the iommu_resv_type along with reserved regions in new ioctl?

Thanks
Nic

> From: Nicolin Chen <nicolinc@nvidia.com>
> Sent: Tuesday, June 27, 2023 1:29 AM
> 
> > I'm not sure whether the MSI region needs a special MSI type or
> > just a general RESV_DIRECT type for 1:1 mapping, though.
> 
> I don't quite get this part. Isn't MSI having IOMMU_RESV_MSI
> and IOMMU_RESV_SW_MSI? Or does it juset mean we should report
> the iommu_resv_type along with reserved regions in new ioctl?
> 

Currently those are iommu internal types. When defining the new
ioctl we need think about what are necessary presenting to the user.

Probably just a list of reserved regions plus a flag to mark which
one is SW_MSI? Except SW_MSI all other reserved region types
just need the user to reserve them w/o knowing more detail.

On Tue, Jun 27, 2023 at 06:02:13AM +0000, Tian, Kevin wrote:
> > From: Nicolin Chen <nicolinc@nvidia.com>
> > Sent: Tuesday, June 27, 2023 1:29 AM
> > 
> > > I'm not sure whether the MSI region needs a special MSI type or
> > > just a general RESV_DIRECT type for 1:1 mapping, though.
> > 
> > I don't quite get this part. Isn't MSI having IOMMU_RESV_MSI
> > and IOMMU_RESV_SW_MSI? Or does it juset mean we should report
> > the iommu_resv_type along with reserved regions in new ioctl?
> > 
> 
> Currently those are iommu internal types. When defining the new
> ioctl we need think about what are necessary presenting to the user.
> 
> Probably just a list of reserved regions plus a flag to mark which
> one is SW_MSI? Except SW_MSI all other reserved region types
> just need the user to reserve them w/o knowing more detail.

I think I prefer the idea we just import the reserved regions from a
devid and do not expose any of this detail to userspace.

Kernel can make only the SW_MSI a mandatory cut out when the S2 is
attached.

Jason

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Wednesday, June 28, 2023 12:01 AM
> 
> On Tue, Jun 27, 2023 at 06:02:13AM +0000, Tian, Kevin wrote:
> > > From: Nicolin Chen <nicolinc@nvidia.com>
> > > Sent: Tuesday, June 27, 2023 1:29 AM
> > >
> > > > I'm not sure whether the MSI region needs a special MSI type or
> > > > just a general RESV_DIRECT type for 1:1 mapping, though.
> > >
> > > I don't quite get this part. Isn't MSI having IOMMU_RESV_MSI
> > > and IOMMU_RESV_SW_MSI? Or does it juset mean we should report
> > > the iommu_resv_type along with reserved regions in new ioctl?
> > >
> >
> > Currently those are iommu internal types. When defining the new
> > ioctl we need think about what are necessary presenting to the user.
> >
> > Probably just a list of reserved regions plus a flag to mark which
> > one is SW_MSI? Except SW_MSI all other reserved region types
> > just need the user to reserve them w/o knowing more detail.
> 
> I think I prefer the idea we just import the reserved regions from a
> devid and do not expose any of this detail to userspace.
> 
> Kernel can make only the SW_MSI a mandatory cut out when the S2 is
> attached.
> 

I'm confused.

The VMM needs to know reserved regions per dev_id and report them
to the guest.

And we have aligned on that reserved regions (except SW_MSI) should
not be automatically added to S2 in nesting case. Then the VMM cannot
rely on IOAS_IOVA_RANGES to identify the reserved regions.

So there needs a new interface for the user to discover reserved regions
per dev_id, within which the SW_MSI region should be marked out so
identity mapping can be installed properly for it in S1.

Did I misunderstand your point in previous discussion?

On Wed, Jun 28, 2023 at 02:47:02AM +0000, Tian, Kevin wrote:
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > Sent: Wednesday, June 28, 2023 12:01 AM
> > 
> > On Tue, Jun 27, 2023 at 06:02:13AM +0000, Tian, Kevin wrote:
> > > > From: Nicolin Chen <nicolinc@nvidia.com>
> > > > Sent: Tuesday, June 27, 2023 1:29 AM
> > > >
> > > > > I'm not sure whether the MSI region needs a special MSI type or
> > > > > just a general RESV_DIRECT type for 1:1 mapping, though.
> > > >
> > > > I don't quite get this part. Isn't MSI having IOMMU_RESV_MSI
> > > > and IOMMU_RESV_SW_MSI? Or does it juset mean we should report
> > > > the iommu_resv_type along with reserved regions in new ioctl?
> > > >
> > >
> > > Currently those are iommu internal types. When defining the new
> > > ioctl we need think about what are necessary presenting to the user.
> > >
> > > Probably just a list of reserved regions plus a flag to mark which
> > > one is SW_MSI? Except SW_MSI all other reserved region types
> > > just need the user to reserve them w/o knowing more detail.
> > 
> > I think I prefer the idea we just import the reserved regions from a
> > devid and do not expose any of this detail to userspace.
> > 
> > Kernel can make only the SW_MSI a mandatory cut out when the S2 is
> > attached.
> > 
> 
> I'm confused.
> 
> The VMM needs to know reserved regions per dev_id and report them
> to the guest.
> 
> And we have aligned on that reserved regions (except SW_MSI) should
> not be automatically added to S2 in nesting case. Then the VMM cannot
> rely on IOAS_IOVA_RANGES to identify the reserved regions.

We also said we need a way to load the reserved regions to create an
identity compatible version of the HWPT

So we have a model where the VMM will want to load in regions beyond
the currently attached device needs

> So there needs a new interface for the user to discover reserved regions
> per dev_id, within which the SW_MSI region should be marked out so
> identity mapping can be installed properly for it in S1.
> 
> Did I misunderstand your point in previous discussion?

This is another discussion, if the vmm needs this then we probably
need a new API to get it.

Jason

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Wednesday, June 28, 2023 8:36 PM
> 
> On Wed, Jun 28, 2023 at 02:47:02AM +0000, Tian, Kevin wrote:
> > > From: Jason Gunthorpe <jgg@nvidia.com>
> > > Sent: Wednesday, June 28, 2023 12:01 AM
> > >
> > > On Tue, Jun 27, 2023 at 06:02:13AM +0000, Tian, Kevin wrote:
> > > > > From: Nicolin Chen <nicolinc@nvidia.com>
> > > > > Sent: Tuesday, June 27, 2023 1:29 AM
> > > > >
> > > > > > I'm not sure whether the MSI region needs a special MSI type or
> > > > > > just a general RESV_DIRECT type for 1:1 mapping, though.
> > > > >
> > > > > I don't quite get this part. Isn't MSI having IOMMU_RESV_MSI
> > > > > and IOMMU_RESV_SW_MSI? Or does it juset mean we should report
> > > > > the iommu_resv_type along with reserved regions in new ioctl?
> > > > >
> > > >
> > > > Currently those are iommu internal types. When defining the new
> > > > ioctl we need think about what are necessary presenting to the user.
> > > >
> > > > Probably just a list of reserved regions plus a flag to mark which
> > > > one is SW_MSI? Except SW_MSI all other reserved region types
> > > > just need the user to reserve them w/o knowing more detail.
> > >
> > > I think I prefer the idea we just import the reserved regions from a
> > > devid and do not expose any of this detail to userspace.
> > >
> > > Kernel can make only the SW_MSI a mandatory cut out when the S2 is
> > > attached.
> > >
> >
> > I'm confused.
> >
> > The VMM needs to know reserved regions per dev_id and report them
> > to the guest.
> >
> > And we have aligned on that reserved regions (except SW_MSI) should
> > not be automatically added to S2 in nesting case. Then the VMM cannot
> > rely on IOAS_IOVA_RANGES to identify the reserved regions.
> 
> We also said we need a way to load the reserved regions to create an
> identity compatible version of the HWPT
> 
> So we have a model where the VMM will want to load in regions beyond
> the currently attached device needs

No question on this.

> 
> > So there needs a new interface for the user to discover reserved regions
> > per dev_id, within which the SW_MSI region should be marked out so
> > identity mapping can be installed properly for it in S1.
> >
> > Did I misunderstand your point in previous discussion?
> 
> This is another discussion, if the vmm needs this then we probably
> need a new API to get it.
> 

Then it's clear. 😊

On Mon, Jun 26, 2023 at 06:42:58AM +0000, Tian, Kevin wrote:

> I'm not sure whether the MSI region needs a special MSI type or
> just a general RESV_DIRECT type for 1:1 mapping, though.

It probably always needs a special type :(

Jason

On Wed, Jun 21, 2023 at 06:02:21AM +0000, Tian, Kevin wrote:
> > > My understanding of ARM SMMU is that from host p.o.v. the CD is the
> > > S1 in the nested configuration. 'identity' is one configuration in the CD
> > > then it's in the business of nesting.
> > 
> > I think it is the same. A CD doesn't come into the picture until the
> > guest installs a CD pointing STE. Until that time the S2 is being used
> > as identity.
> > 
> > It sounds like the same basic flow.
> 
> After a CD table is installed in a STE I assume the SMMU still allows to
> configure an individual CD entry as identity? e.g. while vSVA is enabled
> on a device the guest can continue to keep CD#0 as identity when the
> default domain of the device is set as 'passthrough'. In this case the
> IOAS still needs to gain reserved regions even though S2 is not directly
> attached from host p.o.v.

In any nesting configuration the hypervisor cannot directly restrict
what IOVA the guest will use. The VM could make a normal nest and try
to use unusable IOVA. Identity is not really special.

The VMM should construct the guest memory map so that an identity
iommu_domain can meet the reserved requirements - it needs to do this
anyhow for the initial boot part. It shouuld try to forward the
reserved regions to the guest via ACPI/etc.

Being able to explicitly load reserved regions into an IOAS seems like
a useful way to help construct this.

Jason

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Wednesday, June 21, 2023 8:05 PM
> 
> On Wed, Jun 21, 2023 at 06:02:21AM +0000, Tian, Kevin wrote:
> > > > My understanding of ARM SMMU is that from host p.o.v. the CD is the
> > > > S1 in the nested configuration. 'identity' is one configuration in the CD
> > > > then it's in the business of nesting.
> > >
> > > I think it is the same. A CD doesn't come into the picture until the
> > > guest installs a CD pointing STE. Until that time the S2 is being used
> > > as identity.
> > >
> > > It sounds like the same basic flow.
> >
> > After a CD table is installed in a STE I assume the SMMU still allows to
> > configure an individual CD entry as identity? e.g. while vSVA is enabled
> > on a device the guest can continue to keep CD#0 as identity when the
> > default domain of the device is set as 'passthrough'. In this case the
> > IOAS still needs to gain reserved regions even though S2 is not directly
> > attached from host p.o.v.
> 
> In any nesting configuration the hypervisor cannot directly restrict
> what IOVA the guest will use. The VM could make a normal nest and try
> to use unusable IOVA. Identity is not really special.

Sure. What I talked is the end result e.g. after the user explicitly requests
to load reserved regions into an IOAS.

> 
> The VMM should construct the guest memory map so that an identity
> iommu_domain can meet the reserved requirements - it needs to do this
> anyhow for the initial boot part. It shouuld try to forward the
> reserved regions to the guest via ACPI/etc.

Yes.

> 
> Being able to explicitly load reserved regions into an IOAS seems like
> a useful way to help construct this.
> 

And it's correct in concept because the IOAS is 'implicitly' accessed by
the device when the guest domain is identity in this case.

> From: Tian, Kevin <kevin.tian@intel.com>
> Sent: Wednesday, June 21, 2023 2:02 PM
> 
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > Sent: Tuesday, June 20, 2023 8:47 PM
> >
> > On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
> > > I wonder whether we have argued passed each other.
> > >
> > > This series adds reserved regions to S2. I challenged the necessity as
> > > S2 is not directly accessed by the device.
> > >
> > > Then you replied that doing so still made sense to support identity
> > > S1.
> >
> > I think I said/ment if we attach the "s2" iommu domain as a direct
> > attach for identity - eg at boot time, then the IOAS must gain the
> > reserved regions. This is our normal protocol.
> >
> > But when we use the "s2" iommu domain as an actual nested S2 then we
> > don't gain reserved regions.
> 
> Then we're aligned.
> 
> Yi/Nicolin, please update this series to not automatically add reserved
> regions to S2 in the nesting configuration.

Got it.

> It also implies that the user cannot rely on IOAS_IOVA_RANGES to
> learn reserved regions for arranging addresses in S1.
> 
> Then we also need a new ioctl to report reserved regions per dev_id.

Shall we add it now? I suppose yes.

> >
> > > Intel VT-d supports 4 configurations:
> > >   - passthrough (i.e. identity mapped)
> > >   - S1 only
> > >   - S2 only
> > >   - nested
> > >
> > > 'S2 only' is used when vIOMMU is configured in passthrough.
> >
> > S2 only is modeled as attaching an S2 format iommu domain to the RID,
> > and when this is done the IOAS should gain the reserved regions
> > because it is no different behavior than attaching any other iommu
> > domain to a RID.
> >
> > When the S2 is replaced with a S1 nest then the IOAS should loose
> > those reserved regions since it is no longer attached to a RID.
> 
> yes

Makes sense.

Regards,
Yi Liu

> 
> >
> > > My understanding of ARM SMMU is that from host p.o.v. the CD is the
> > > S1 in the nested configuration. 'identity' is one configuration in the CD
> > > then it's in the business of nesting.
> >
> > I think it is the same. A CD doesn't come into the picture until the
> > guest installs a CD pointing STE. Until that time the S2 is being used
> > as identity.
> >
> > It sounds like the same basic flow.
> 
> After a CD table is installed in a STE I assume the SMMU still allows to
> configure an individual CD entry as identity? e.g. while vSVA is enabled
> on a device the guest can continue to keep CD#0 as identity when the
> default domain of the device is set as 'passthrough'. In this case the
> IOAS still needs to gain reserved regions even though S2 is not directly
> attached from host p.o.v.
> 
> >
> > > My preference was that ALLOC_HWPT allows vIOMMU to opt whether
> > > reserved regions of dev_id should be added to the IOAS of the parent
> > > S2 hwpt.
> >
> > Having an API to explicitly load reserved regions of a specific device
> > to an IOAS makes some sense to me.
> >
> > Jason

>-----Original Message-----
>From: Jason Gunthorpe <jgg@nvidia.com>
>Sent: Tuesday, June 20, 2023 8:47 PM
>Subject: Re: [PATCH v2 00/11] iommufd: Add nesting infrastructure
>
>On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
>> I wonder whether we have argued passed each other.
>>
>> This series adds reserved regions to S2. I challenged the necessity as
>> S2 is not directly accessed by the device.
>>
>> Then you replied that doing so still made sense to support identity
>> S1.
>
>I think I said/ment if we attach the "s2" iommu domain as a direct attach for
>identity - eg at boot time, then the IOAS must gain the reserved regions. This is
>our normal protocol.
There is code to fail the attaching for device with RMRR in intel iommu driver,
do we plan to remove below check for IOMMUFD soon or later?

static int intel_iommu_attach_device(struct iommu_domain *domain,
                                     struct device *dev)
{
        struct device_domain_info *info = dev_iommu_priv_get(dev);
        int ret;

        if (domain->type == IOMMU_DOMAIN_UNMANAGED &&
            device_is_rmrr_locked(dev)) {
                dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement.  Contact your platform vendor.\n");
                return -EPERM;
        }

Thanks
Zhenzhong

On Wed, Jun 21, 2023 at 08:29:09AM +0000, Duan, Zhenzhong wrote:
> >-----Original Message-----
> >From: Jason Gunthorpe <jgg@nvidia.com>
> >Sent: Tuesday, June 20, 2023 8:47 PM
> >Subject: Re: [PATCH v2 00/11] iommufd: Add nesting infrastructure
> >
> >On Tue, Jun 20, 2023 at 01:43:42AM +0000, Tian, Kevin wrote:
> >> I wonder whether we have argued passed each other.
> >>
> >> This series adds reserved regions to S2. I challenged the necessity as
> >> S2 is not directly accessed by the device.
> >>
> >> Then you replied that doing so still made sense to support identity
> >> S1.
> >
> >I think I said/ment if we attach the "s2" iommu domain as a direct attach for
> >identity - eg at boot time, then the IOAS must gain the reserved regions. This is
> >our normal protocol.
> There is code to fail the attaching for device with RMRR in intel iommu driver,
> do we plan to remove below check for IOMMUFD soon or later?
> 
> static int intel_iommu_attach_device(struct iommu_domain *domain,
>                                      struct device *dev)
> {
>         struct device_domain_info *info = dev_iommu_priv_get(dev);
>         int ret;
> 
>         if (domain->type == IOMMU_DOMAIN_UNMANAGED &&
>             device_is_rmrr_locked(dev)) {
>                 dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement.  Contact your platform vendor.\n");
>                 return -EPERM;
>         }

Not really, systems with RMRR cannot support VFIO at all. Baolu sent a
series lifting this restriction up higher in the stack:

https://lore.kernel.org/all/20230607035145.343698-1-baolu.lu@linux.intel.com/

Jason