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[PATCH v2] riscv: vector: Fix context save/restore with xtheadvector

Han Gao posted 1 patch 7 months ago 
arch/riscv/include/asm/vector.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
[PATCH v2] riscv: vector: Fix context save/restore with xtheadvector
Posted by Han Gao 7 months ago 
Previously only v0-v7 were correctly saved/restored,
and the context of v8-v31 are damanged.
Correctly save/restore v8-v31 to avoid breaking userspace.

Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
---

Changes in v2:
  Add fix tag
  Improve commit mesage

v1: https://lore.kernel.org/linux-riscv/c221c98dc2369ea691e3eb664bf084dc909496f6.1747934680.git.rabenda.cn@gmail.com/

 arch/riscv/include/asm/vector.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index e8a83f55be2b..7df6355023a3 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
 			THEAD_VSETVLI_T4X0E8M8D1
 			THEAD_VSB_V_V0T0
 			"add		t0, t0, t4\n\t"
-			THEAD_VSB_V_V0T0
+			THEAD_VSB_V_V8T0
 			"add		t0, t0, t4\n\t"
-			THEAD_VSB_V_V0T0
+			THEAD_VSB_V_V16T0
 			"add		t0, t0, t4\n\t"
-			THEAD_VSB_V_V0T0
+			THEAD_VSB_V_V24T0
 			: : "r" (datap) : "memory", "t0", "t4");
 	} else {
 		asm volatile (
@@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
 			THEAD_VSETVLI_T4X0E8M8D1
 			THEAD_VLB_V_V0T0
 			"add		t0, t0, t4\n\t"
-			THEAD_VLB_V_V0T0
+			THEAD_VLB_V_V8T0
 			"add		t0, t0, t4\n\t"
-			THEAD_VLB_V_V0T0
+			THEAD_VLB_V_V16T0
 			"add		t0, t0, t4\n\t"
-			THEAD_VLB_V_V0T0
+			THEAD_VLB_V_V24T0
 			: : "r" (datap) : "memory", "t0", "t4");
 	} else {
 		asm volatile (
-- 
2.47.2
Re: [PATCH v2] riscv: vector: Fix context save/restore with xtheadvector
Posted by Yanteng Si 6 months, 3 weeks ago 
在 5/23/25 6:25 PM, Han Gao 写道:
> Previously only v0-v7 were correctly saved/restored,
> and the context of v8-v31 are damanged.
> Correctly save/restore v8-v31 to avoid breaking userspace.
> 
> Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Yanteng Si <si.yanteng@linux.dev>

Thanks,
Yanteng
> ---
> 
> Changes in v2:
>    Add fix tag
>    Improve commit mesage
> 
> v1: https://lore.kernel.org/linux-riscv/c221c98dc2369ea691e3eb664bf084dc909496f6.1747934680.git.rabenda.cn@gmail.com/
> 
>   arch/riscv/include/asm/vector.h | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index e8a83f55be2b..7df6355023a3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
>   			THEAD_VSETVLI_T4X0E8M8D1
>   			THEAD_VSB_V_V0T0
>   			"add		t0, t0, t4\n\t"
> -			THEAD_VSB_V_V0T0
> +			THEAD_VSB_V_V8T0
>   			"add		t0, t0, t4\n\t"
> -			THEAD_VSB_V_V0T0
> +			THEAD_VSB_V_V16T0
>   			"add		t0, t0, t4\n\t"
> -			THEAD_VSB_V_V0T0
> +			THEAD_VSB_V_V24T0
>   			: : "r" (datap) : "memory", "t0", "t4");
>   	} else {
>   		asm volatile (
> @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
>   			THEAD_VSETVLI_T4X0E8M8D1
>   			THEAD_VLB_V_V0T0
>   			"add		t0, t0, t4\n\t"
> -			THEAD_VLB_V_V0T0
> +			THEAD_VLB_V_V8T0
>   			"add		t0, t0, t4\n\t"
> -			THEAD_VLB_V_V0T0
> +			THEAD_VLB_V_V16T0
>   			"add		t0, t0, t4\n\t"
> -			THEAD_VLB_V_V0T0
> +			THEAD_VLB_V_V24T0
>   			: : "r" (datap) : "memory", "t0", "t4");
>   	} else {
>   		asm volatile (
Re: [PATCH v2] riscv: vector: Fix context save/restore with xtheadvector
Posted by Andy Chiu 6 months, 4 weeks ago 
On Fri, May 23, 2025 at 6:26 PM Han Gao <rabenda.cn@gmail.com> wrote:
>
> Previously only v0-v7 were correctly saved/restored,
> and the context of v8-v31 are damanged.
> Correctly save/restore v8-v31 to avoid breaking userspace.
>
> Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>

Reviewed-by: Andy Chiu <andybnac@gmail.com>

> ---
>
> Changes in v2:
>   Add fix tag
>   Improve commit mesage
>
> v1: https://lore.kernel.org/linux-riscv/c221c98dc2369ea691e3eb664bf084dc909496f6.1747934680.git.rabenda.cn@gmail.com/
>
>  arch/riscv/include/asm/vector.h | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index e8a83f55be2b..7df6355023a3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
>                         THEAD_VSETVLI_T4X0E8M8D1
>                         THEAD_VSB_V_V0T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VSB_V_V0T0
> +                       THEAD_VSB_V_V8T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VSB_V_V0T0
> +                       THEAD_VSB_V_V16T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VSB_V_V0T0
> +                       THEAD_VSB_V_V24T0
>                         : : "r" (datap) : "memory", "t0", "t4");
>         } else {
>                 asm volatile (
> @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
>                         THEAD_VSETVLI_T4X0E8M8D1
>                         THEAD_VLB_V_V0T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VLB_V_V0T0
> +                       THEAD_VLB_V_V8T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VLB_V_V0T0
> +                       THEAD_VLB_V_V16T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VLB_V_V0T0
> +                       THEAD_VLB_V_V24T0
>                         : : "r" (datap) : "memory", "t0", "t4");
>         } else {
>                 asm volatile (
> --
> 2.47.2
>

Patchew 2.1-devel-b67e4c2

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