arch/mips/cobalt/pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE
controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and
0x3f6. These resources cannot be claimed under the host bridge window.
Since pcibios_enable_device() was converted to pci_enable_resources(),
the unclaimed IDE resources cause device enable to fail with -EINVAL:
pata_via 0000:00:09.1: BAR 0 [io 0x01f0-0x01f7]: not claimed; can't enable device
pata_via 0000:00:09.1: probe with driver pata_via failed with error -22
Lower the PCI I/O window start to 0x100 so the fixed IDE resources can
be claimed. Keep the reserved ISA resources below 0x100 outside the PCI
window.
On Qube2, the relevant I/O resources change as follows:
Before After
Host bridge window 1000-ffffff 0100-ffffff
IDE BARs 0-3 Outside window Inside window
IDE BAR 4 (DMA) 1420-142f 0820-082f
With the fix, both pata_via hosts initialize and the ST380012A 80 GB
hard disk is detected as sda. The MIPS64 kernel reaches a root shell and
passes all eight boot-smoke checks.
Fixes: ae81aad5c2e1 ("MIPS: PCI: Use pci_enable_resources()")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/mips/cobalt/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c
index 85ec9cc31d66..293c02e151d3 100644
--- a/arch/mips/cobalt/pci.c
+++ b/arch/mips/cobalt/pci.c
@@ -24,7 +24,8 @@ static struct resource cobalt_mem_resource = {
};
static struct resource cobalt_io_resource = {
- .start = 0x1000,
+ /* Include legacy IDE ports, but exclude the reserved ISA ports. */
+ .start = 0x100,
.end = 0xffffffUL,
.name = "PCI I/O",
.flags = IORESOURCE_IO,
--
2.53.0On Thu, 15 Oct 2026, Florian Fainelli wrote: > The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE > controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and > 0x3f6. These resources cannot be claimed under the host bridge window. > > Since pcibios_enable_device() was converted to pci_enable_resources(), > the unclaimed IDE resources cause device enable to fail with -EINVAL: > > pata_via 0000:00:09.1: BAR 0 [io 0x01f0-0x01f7]: not claimed; can't enable device > pata_via 0000:00:09.1: probe with driver pata_via failed with error -22 > > Lower the PCI I/O window start to 0x100 so the fixed IDE resources can > be claimed. Keep the reserved ISA resources below 0x100 outside the PCI > window. Why not go with 0 (unless that's not what the system controller supports as the bottom of the PCI I/O space), and just set PCIBIOS_MIN_IO correctly as several platforms do instead? Is there a southbridge in your system? Maciej
On 10/20/26 10:13, Maciej W. Rozycki wrote: > On Thu, 15 Oct 2026, Florian Fainelli wrote: > >> The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE >> controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and >> 0x3f6. These resources cannot be claimed under the host bridge window. >> >> Since pcibios_enable_device() was converted to pci_enable_resources(), >> the unclaimed IDE resources cause device enable to fail with -EINVAL: >> >> pata_via 0000:00:09.1: BAR 0 [io 0x01f0-0x01f7]: not claimed; can't enable device >> pata_via 0000:00:09.1: probe with driver pata_via failed with error -22 >> >> Lower the PCI I/O window start to 0x100 so the fixed IDE resources can >> be claimed. Keep the reserved ISA resources below 0x100 outside the PCI >> window. > > Why not go with 0 (unless that's not what the system controller supports > as the bottom of the PCI I/O space), and just set PCIBIOS_MIN_IO correctly > as several platforms do instead? Is there a southbridge in your system? 0 does not work and gives me: [ 0.205993] Skipping PCI bus scan due to resource conflict There is no south bridge AFAICT, the CPU connection to the GT-64111. -- Florian
On Wed, 21 Oct 2026, Florian Fainelli wrote:
> > > Lower the PCI I/O window start to 0x100 so the fixed IDE resources can
> > > be claimed. Keep the reserved ISA resources below 0x100 outside the PCI
> > > window.
> >
> > Why not go with 0 (unless that's not what the system controller supports
> > as the bottom of the PCI I/O space), and just set PCIBIOS_MIN_IO correctly
> > as several platforms do instead? Is there a southbridge in your system?
>
> 0 does not work and gives me:
>
> [ 0.205993] Skipping PCI bus scan due to resource conflict
>
> There is no south bridge AFAICT, the CPU connection to the GT-64111.
Thanks. The Galileo is the northbridge. The conflict is due to:
/* These resources have been reserved by VIA SuperI/O chip. */
for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
request_resource(&ioport_resource, cobalt_reserved_resources + i);
which clearly functions as the southbridge (there's also:
* Also PCI-ISA bridge DMA controller is never used.
earlier on) and these resources belong to PCI really. What does:
$ lspci -nn
say?
We had a similar regression with the Malta, except the resources were
claimed in the other order and therefore fixed in a straightforward way
with commit 1d5d1663619d ("MIPS: Malta: Fix PCI southbridge legacy
resource reservations"). Consequently /proc/ioport map now looks like:
00000000-00ffffff : MSC PCI I/O
00000000-0000001f : dma1
00000020-00000021 : pic1
00000040-0000005f : timer
00000060-0000006f : keyboard
00000060-0000006f : i8042
00000070-00000077 : rtc0
00000080-0000008f : dma page reg
000000a0-000000a1 : pic2
000000c0-000000df : dma2
00000170-00000177 : 0000:00:0a.1
00000170-00000177 : ata_piix
000001f0-000001f7 : 0000:00:0a.1
000001f0-000001f7 : ata_piix
000002f8-000002ff : serial
00000376-00000376 : 0000:00:0a.1
00000376-00000376 : ata_piix
00000378-0000037a : parport0
0000037b-0000037f : parport0
000003f2-000003f2 : floppy
000003f4-000003f5 : floppy
000003f6-000003f6 : 0000:00:0a.1
000003f6-000003f6 : ata_piix
000003f7-000003f7 : floppy
000003f8-000003ff : serial
00001000-0000103f : 0000:00:0a.3
00001040-0000105f : 0000:00:0a.2
00001040-0000105f : uhci_hcd
00001060-0000107f : 0000:00:0b.0
00001060-0000107f : pcnet32_probe_pci
00001080-000010ff : 0000:00:12.0
00001100-0000110f : 0000:00:0a.3
00001400-000014ff : 0000:00:13.0
00001800-0000180f : 0000:00:0a.1
00001800-0000180f : ata_piix
Previously it looked (incorrectly) like:
00000000-0000001f : dma1
00000020-00000021 : pic1
00000040-0000005f : timer
00000060-0000006f : keyboard
00000070-00000077 : rtc0
00000080-0000008f : dma page reg
000000a0-000000a1 : pic2
000000c0-000000df : dma2
00000170-00000177 : ata_piix
000001f0-000001f7 : ata_piix
000002f8-000002ff : serial
00000376-00000376 : ata_piix
00000378-0000037a : parport0
0000037b-0000037f : parport0
000003f6-000003f6 : ata_piix
000003f8-000003ff : serial
00001000-001fffff : GT-64120 PCI I/O
00001000-0000103f : 0000:00:0a.3
00001040-0000105f : 0000:00:0a.2
00001060-0000107f : 0000:00:0b.0
00001060-0000107f : pcnet32_probe_pci
00001080-000010ff : 0000:00:14.0
00001100-0000110f : 0000:00:0a.3
00001400-000014ff : 0000:00:13.0
00001800-0000180f : 0000:00:0a.1
00001800-0000180f : ata_piix
(I've lost the Galileo module, so the output isn't exactly like-for-like).
Note the old I/O start address of 00001000, exactly as with your system.
Also note the fixed i8042 driver registration; this is owing to commit
bf5570590a98 ("MIPS: Malta: Fix keyboard resource preventing i8042 driver
from registering"), but I guess you won't need such a change because:
* Cobalt doesn't have PS/2 keyboard/mouse interfaces,
* keyboard controller is never used.
I'd suggest that you get this right and swap the ordering of resource
requests by registering the PCI controller first too, possibly by moving
southbridge resource reservations to cobalt_pci_init(), and similarly
using insert_resource() rather than request_resource().
NB if you had no southbridge at all, then you could use PCIBIOS_MIN_IO of
4; cf. commit bb356ddb78b2 ("RISC-V: PCI: Avoid handing out address 0 to
devices"). Otherwise moving the existing allocation base of 0x1000 there
seems the proper way.
Maciej
© 2016 - 2026 Red Hat, Inc.