Tegra PCIe endpoint controllers are platform devices and issue DMA as SoC
masters. Attach them directly to the SMMU with an iommus property so the
platform device gets an IOMMU fwspec and domain during probe.

The endpoint controllers supported by the Tegra194/234 PCIe driver expose a
single endpoint function. They do not need iommu-map or iommu-map-mask
properties because there is no endpoint function/device ID mapping to
express. Those properties also do not attach the endpoint controller
platform device itself to the SMMU.

Use direct iommus properties for the Tegra194 and Tegra234 PCIe endpoint
nodes and remove the unnecessary iommu-map properties from those nodes.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi |  9 +++------
 arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++--------
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 5e510f77b538..a7843bae02ac 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2596,8 +2596,7 @@ pcie-ep@14160000 {
 			interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
 					<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu TEGRA194_SID_PCIE4>;
 			dma-coherent;
 		};
 
@@ -2689,8 +2688,7 @@ pcie-ep@14180000 {
 			interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
 					<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu TEGRA194_SID_PCIE0>;
 			dma-coherent;
 		};
 
@@ -2788,8 +2786,7 @@ pcie-ep@141a0000 {
 			interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
 					<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu TEGRA194_SID_PCIE5>;
 			dma-coherent;
 		};
 
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 5e29316a4d75..6fb2ff1253c4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4694,8 +4694,7 @@ pcie-ep@140e0000 {
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
 			dma-coherent;
 
 			status = "disabled";
@@ -5099,8 +5098,7 @@ pcie-ep@141a0000 {
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>;
 			dma-coherent;
 
 			status = "disabled";
@@ -5195,8 +5193,7 @@ pcie-ep@141c0000 {
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>;
 			dma-coherent;
 
 			status = "disabled";
@@ -5291,8 +5288,7 @@ pcie-ep@141e0000 {
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
 			interconnect-names = "dma-mem", "write";
-			iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
-			iommu-map-mask = <0x0>;
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>;
 			dma-coherent;
 
 			status = "disabled";
-- 
2.34.1