From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

After a bad bitstream, the CFG_RDY poll at the end of teardown can time
out because CVP_STATUS gets stuck. This series exits CvP mode to switch
back the clock feeding CVP_STATUS and retries the teardown once.

Patch 1 factors out the existing CVP_MODE/HIP_CLK_SEL clearing into a
helper. Patch 2 uses it in the new teardown recovery path.

v2: https://lore.kernel.org/linux-fpga/20260915062734.42964-1-muhammad.nazim.amirul.nazle.asmade@altera.com/
v1: https://lore.kernel.org/linux-fpga/20260618112410.303-1-muhammad.nazim.amirul.nazle.asmade@altera.com/

Changes in v3:
- Split altera_cvp_disable_cvp_mode() into a preparatory patch and use
  it for STEP 17 in altera_cvp_write_complete()
- Drop CVP_TEARDOWN_MAX_RETRY and the loop; retry once directly
- Add a comment explaining why the retry is done
- Drop the retry count from the failure message
- Drop the success message

Changes in v2:
- Rewrite commit message to explain CFG_RDY timeout, HIP clock switch,
  and why one retry is enough
- Move CvP mode/HIP clock cleanup into recovery via
  altera_cvp_disable_cvp_mode() helper
- Reduce retries to 1 (first teardown + one retry after cleanup)
- Use dev_warn for per-teardown CFG_RDY timeout; one final
  success/failure message from recovery

Nazim Amirul (2):
  fpga: altera-cvp: Add helper to disable CvP mode
  fpga: altera-cvp: Retry teardown and reset CVP state on failure

 drivers/fpga/altera-cvp.c | 43 ++++++++++++++++++++++++++++++++-------
 1 file changed, 36 insertions(+), 7 deletions(-)

-- 
2.43.7