From: Chi-Wen Weng <cwweng@nuvoton.com>

This series adds Devicetree binding and driver support for the SPI
controller found in the Nuvoton MA35D1 SoC.

The driver implements SPI host mode using polling-based PIO transfers.
It supports SPI modes 0 through 3, LSB-first operation, and word sizes
from 8 to 32 bits.

The controller provides two native chip-select outputs. GPIO chip
selects are also supported through the SPI core GPIO descriptor
infrastructure.

The driver programs the clock divider according to the hardware
requirement that only odd CLKDIV register values are valid, and rounds
the divisor so that the generated SPI clock does not exceed the
requested transfer frequency.

DMA, target mode, half-duplex, 3-wire operation, FIFO threshold
interrupt transfers, and the I2S function sharing the same hardware
block are not included in this initial version.

Patch 1 adds the Devicetree binding.
Patch 2 adds the MA35D1 SPI controller driver.

Chi-Wen Weng (2):
  dt-bindings: spi: nuvoton,ma35d1-spi: Add Nuvoton MA35D1 SPI
    controller
  spi: ma35d1: Add Nuvoton MA35D1 SPI controller support

 .../bindings/spi/nuvoton,ma35d1-spi.yaml      |  70 ++
 drivers/spi/Kconfig                           |  11 +
 drivers/spi/Makefile                          |   1 +
 drivers/spi/spi-ma35d1.c                      | 701 ++++++++++++++++++
 4 files changed, 783 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,ma35d1-spi.yaml
 create mode 100644 drivers/spi/spi-ma35d1.c

-- 
2.25.1