ZynqMP NAND controller nodes contain "num-cs" and "power-domains"
properties. Add num-cs with a range of one to two chip selects and allow
one power-domain.
Assisted-by: LLM
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
.../devicetree/bindings/mtd/arasan,nand-controller.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml
index b90d3b48c2f2..4262996dd51e 100644
--- a/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml
@@ -35,6 +35,14 @@ properties:
interrupts:
maxItems: 1
+ num-cs:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 2
+
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
--
2.53.0