arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 21 +++++++ arch/arm64/boot/dts/qcom/nord.dtsi | 67 +++++++++++++++++++++ 2 files changed, 88 insertions(+)
From: Pushpendra Singh <pussin@qti.qualcomm.com>
Add BWMON nodes and associated OPP tables to enable dynamic DDR/LLCC
frequency scaling.
The compatible is added in nord-embedded.dtsi rather than nord.dtsi,
because Embedded variant specific 'interconnects' is required by
the compatible.
Co-developed-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com>
Signed-off-by: Pushpendra Singh <pussin@qti.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Dependencies:
- BWMON binding: https://lore.kernel.org/all/20260831090134.585588-1-zhangfei.gao@oss.qualcomm.com/
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 21 +++++++
arch/arm64/boot/dts/qcom/nord.dtsi | 67 +++++++++++++++++++++
2 files changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 568fe68cd185..c27d01a82214 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -30,6 +30,27 @@ mc_virt: interconnect-mc-virt {
};
};
+&bwmon_cluster0 {
+ compatible = "qcom,nord-cpu-bwmon",
+ "qcom,sdm845-bwmon";
+ interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+};
+
+&bwmon_cluster1 {
+ compatible = "qcom,nord-cpu-bwmon",
+ "qcom,sdm845-bwmon";
+ interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+};
+
+&bwmon_cluster2 {
+ compatible = "qcom,nord-cpu-bwmon",
+ "qcom,sdm845-bwmon";
+ interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+};
+
&crypto {
interconnects = <&aggre1_noc_tile MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index e0496fd40c30..9925e770dfa4 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1460,6 +1460,73 @@ uart13: serial@a98000 {
};
};
+ bwmon_cluster2: pmu@1014400 {
+ reg = <0x0 0x01014400 0x0 0x600>;
+ interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&bwmon_cluster_opp_table>;
+ };
+
+ bwmon_cluster1: pmu@1015400 {
+ reg = <0x0 0x01015400 0x0 0x600>;
+ interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&bwmon_cluster_opp_table>;
+ };
+
+ bwmon_cluster0: pmu@1016400 {
+ reg = <0x0 0x01016400 0x0 0x600>;
+ interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
+
+ operating-points-v2 = <&bwmon_cluster_opp_table>;
+
+ bwmon_cluster_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <800000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2188800>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <5414400>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <6220800>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <6835200>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <7603200>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <8371200>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <9657600>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <10944000>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <12748800>;
+ };
+
+ opp-10 {
+ opp-peak-kBps = <14745600>;
+ };
+ };
+ };
+
rng: rng@10c3000 {
compatible = "qcom,nord-trng",
"qcom,trng";
--
2.43.0On 9/22/26 10:04 AM, Shawn Guo wrote:
> From: Pushpendra Singh <pussin@qti.qualcomm.com>
>
> Add BWMON nodes and associated OPP tables to enable dynamic DDR/LLCC
> frequency scaling.
[...]
> + bwmon_cluster2: pmu@1014400 {
> + reg = <0x0 0x01014400 0x0 0x600>;
len=0x500 for all the region is 0x600-long, but the docs say
it starts 0x100 earlier (with registers actually starting
at +0x400 like your node here) - unless you want to solve that
discrepancy in the driver, but i'm not sure it's worth the
hassle
otherwise
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
On Tue, Sep 22, 2026 at 6:33 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 9/22/26 10:04 AM, Shawn Guo wrote:
> > From: Pushpendra Singh <pussin@qti.qualcomm.com>
> >
> > Add BWMON nodes and associated OPP tables to enable dynamic DDR/LLCC
> > frequency scaling.
>
> [...]
>
> > + bwmon_cluster2: pmu@1014400 {
> > + reg = <0x0 0x01014400 0x0 0x600>;
>
> len=0x500 for all the region is 0x600-long, but the docs say
> it starts 0x100 earlier (with registers actually starting
> at +0x400 like your node here) - unless you want to solve that
> discrepancy in the driver, but i'm not sure it's worth the
> hassle
Oh, good catch, len should be 0x500.
The address is intentionally shifted by 0x100 to remain compatible
with the existing driver.
The driver expects the PMU registers at this offset, so changing the
base address would require updating the driver and could break
compatibility.
>
> otherwise
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Thanks
On Tue, 22 Sep 2026 10:04:16 +0200, Shawn Guo <shengchao.guo@oss.qualcomm.com> said: > From: Pushpendra Singh <pussin@qti.qualcomm.com> > > Add BWMON nodes and associated OPP tables to enable dynamic DDR/LLCC > frequency scaling. > > The compatible is added in nord-embedded.dtsi rather than nord.dtsi, > because Embedded variant specific 'interconnects' is required by > the compatible. > > Co-developed-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> > Signed-off-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> > Signed-off-by: Pushpendra Singh <pussin@qti.qualcomm.com> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> > --- Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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