This series adds CoreSight nodes for the APSS debug block on multiple
QCOM platform, covering ETM, replicator, funnel and TMC ETF devices,
to enable ETM trace on the CPU cores.
The replicator, funnel and TMC ETF nodes in this block sit on the CPU
cluster power rail rather than on a dedicated always-on rail, so they
need a power-domains property pointing at the corresponding CPU cluster
genpd. Exercising this property correctly depends on two related fixes
that are in flight:
- pmdomain/cpuidle-psci: Fix behaviours for CPU PM domains -> applied
https://lore.kernel.org/all/20260914150146.187622-1-ulf.hansson@oss.qualcomm.com/
Without this series, a non-CPU device (like these CoreSight nodes)
attached to a CPU PM domain cannot wake an idle CPU to power the
domain on, so pm_runtime_get on these devices can never succeed.
- coresight: handle runtime PM resume failures
https://lore.kernel.org/all/20260911-b4-coresight-runtime-pm-failures-v1-1-acdf49756e11@qti.qualcomm.com/
Without this fix, CoreSight ignores runtime PM resume errors and
continues to access registers on an unpowered device, which is
exactly what can happen while a CPU PM domain is being woken up.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Jie Gan (4):
arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block
arm64: dts: qcom: sm8750: Add CoreSight nodes for APSS debug block
arm64: dts: qcom: kaanapali: Add CoreSight nodes for APSS debug block
arm64: dts: qcom: glymur: Add CoreSight nodes for APSS debug block
arch/arm64/boot/dts/qcom/glymur.dtsi | 1184 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/hamoa.dtsi | 884 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 567 +++++++++++++++
arch/arm64/boot/dts/qcom/mahua.dtsi | 16 +
arch/arm64/boot/dts/qcom/purwa.dtsi | 12 +
arch/arm64/boot/dts/qcom/sm8750.dtsi | 599 ++++++++++++++++
6 files changed, 3262 insertions(+)
---
base-commit: 5c4d4169604b335c38bbc79bc1fc03042981fc6f
change-id: 20260922-add-etm-devices-for-multiple-qcom-platforms-c165b1c4480f
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>