[PATCH v9 0/2] clk: add support for TI CDCE6214

Sascha Hauer posted 2 patches 3 days, 13 hours ago
.../devicetree/bindings/clock/ti,cdce6214.yaml     |  198 +++
drivers/clk/Kconfig                                |    9 +
drivers/clk/Makefile                               |    1 +
drivers/clk/clk-cdce6214.c                         | 1594 ++++++++++++++++++++
include/dt-bindings/clock/ti,cdce6214.h            |   25 +
5 files changed, 1827 insertions(+)
[PATCH v9 0/2] clk: add support for TI CDCE6214
Posted by Sascha Hauer 3 days, 13 hours ago
The CDCE6214 is a Ultra-Low Power Clock Generator With One PLL, Four
Differential Outputs, Two Inputs, and Internal EEPROM.

This series adds a common clk framework driver for this chip along with
the dt-bindings document. The cdce6214 needs several pins to be
configured for different input/output modes which are abstracted with a
pinctrl driver.

This version fixes several bugs found by the Sashiko AI review of v8,
see the changelog below for details. As the binding changed
non-trivially, the Reviewed-by tags are dropped.

Sascha

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Changes in v9:
- Drop Reviewed-by tags from binding patch due to non-trivial binding changes
- binding: apply per-pin constraints to ti,io-standard instead of the
  non-existent io-standard property (Sashiko)
- binding: reject 0 for ti,cmosp-mode and ti,cmosn-mode (Sashiko)
- binding: disallow duplicate clock-names (Sashiko)
- binding: fix ti,cmosp-mode description (Sashiko)
- binding: reference the pin configuration from pinctrl-0 in the example
  and sort example properties (dt-check-style --mode=strict)
- fix OUT0 parent count, reading past the parent_data array (Sashiko)
- fix OUT0 set_parent writing REF_CH_MUX instead of REFSEL_SW (Sashiko)
- fix OUT0 doubler rate calculation (Sashiko)
- fix LP-HCSL setup for OUT3 and OUT4 writing to wrong registers (Sashiko)
- fix swapped CMOS N/P bits on OUT4 (Sashiko)
- mark unused output mux input invalid instead of falling back to DT
  clock index 0 (Sashiko)
- avoid division by zero for rate 0 and orphaned parents (Sashiko)
- fix PLL rate overflow on 32-bit (Sashiko)
- allow more time for PLL lock (Sashiko)
- write PSA/PSB register value instead of relying on FIELD_PREP()
  truncation (Sashiko)
- match XO property names with binding (ti,xo-cload-femtofarads,
  ti,xo-bias-microamp)
- fix reading back IO standard of PRIREF, SECREF, OUT2 and OUT3
- fix default values of XO pinconf parameters
- drop dead denominator check in PLL set_rate
- Link to v8: https://lore.kernel.org/r/20260909-clk-cdce6214-v8-0-4dfa355c1f65@pengutronix.de

Changes in v8:
- Add reviewed-by tags to binding patch
- Link to v7: https://lore.kernel.org/r/20251001-clk-cdce6214-v7-0-5f8b44da95a5@pengutronix.de

Changes in v7:
- add missing blank line between properties in binding (Rob)
- drop unnecessary #size-cells #address-cells in binding (Rob)
- add vendor prefix to custom properties (Rob)
- Use standard units where appropriate (Rob)
- add dependency to PINCTRL and select GENERIC_PINCONF (0day bot)
- re-add missing SPDX in ti,cdce6214.h
- Link to v6: https://lore.kernel.org/r/20250903-clk-cdce6214-v6-0-b2cc0a6f282b@pengutronix.de

Changes in v6:
- merge split up patches back together (forgot to mention when sending v6)
- use pinctrl subsystem to configure pins
- Link to v5: https://lore.kernel.org/r/20250618-clk-cdce6214-v5-0-9938b8ed0b94@pengutronix.de

Changes in v5:
- Reword commit message for binding patch (Krzysztof)
- Make clock binding yaml simpler (Krzysztof)
- add link to datasheet to driver code (Stephen)
- Drop inclusion of linux/clk.h (Stephen)
- Add missing #include <linux/bitfield.h> (Kernel test robot)
- simplify cdce6214_clk_out0_get_parent() (Stephen)
- Use divider_get_val() where appropriate (Stephen)
- Add Rxx defines for registers (Stephen)
- Add define for magic value 24 (Stephen)
- introduce and use cdce6214_clk_psx_mask() (Stephen)
- Use clamp() instead of open code (Stephen)
- declare const arrays const (Stephen)
- more use of dev_err_probe() (Stephen)
- use determine_rate() instead of round_rate (Stephen)
- split out pin configuration to separate patches
- Link to v4: https://lore.kernel.org/r/20250430-clk-cdce6214-v4-0-9f15e7126ac6@pengutronix.de

Changes in v4:
- add missing '>' modifier in include/dt-bindings/clock/ti,cdce6214.h
- fix clocks maxItems should be 2
- add missing license in include/dt-bindings/clock/ti,cdce6214.h
- Fix checkpatch issues
- Link to v3: https://lore.kernel.org/r/20250410-clk-cdce6214-v3-0-d73cf9ff3d80@pengutronix.de

Changes in v3:
- Use string properties instead of int for enums
- Use units from property-units in dtschema
- Link to v2: https://lore.kernel.org/r/20250409-clk-cdce6214-v2-0-40b25b722ecb@pengutronix.de

Changes in v2:
- Use consistent quotes in binding document
- make clock-names an enum to make each clock fully optional
- drop '|' in binding description where not needed
- encode clock input mode into integer
- encode clock output mode into integer
- do not use defines for reg properties
- support setting load capacity for the oscillator via device tree
- support setting Bias current for the oscillator via device tree
- support setting polarities of CMOS outputs via device tree
- fix compatible string in driver
- remove unused struct cdce6214_config
- Link to v1: https://lore.kernel.org/r/20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de

---
Sascha Hauer (2):
      dt-bindings: clock: add TI CDCE6214 binding
      clk: add TI CDCE6214 clock driver

 .../devicetree/bindings/clock/ti,cdce6214.yaml     |  198 +++
 drivers/clk/Kconfig                                |    9 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk-cdce6214.c                         | 1594 ++++++++++++++++++++
 include/dt-bindings/clock/ti,cdce6214.h            |   25 +
 5 files changed, 1827 insertions(+)
---
base-commit: 93f51579e7df248780214094418f205253383cc5
change-id: 20250408-clk-cdce6214-0c74043dc267

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>