arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 108 ++++++++++++++++++++ 1 file changed, 108 insertions(+)
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add the GPU, camera, video, and display clock controller nodes for
the Qualcomm Nord SoC, along with their required dt-bindings includes.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Resend to separate from Nord display DTS series.
Dependencies:
- Nord base DTS: https://lore.kernel.org/all/20260914031412.140856-1-shengchao.guo@oss.qualcomm.com/
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 108 ++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index c7ac2e66632e..6dc4c871f41e 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -3,7 +3,11 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/clock/qcom,glymur-videocc.h>
+#include <dt-bindings/clock/qcom,nord-camcc.h>
+#include <dt-bindings/clock/qcom,nord-dispcc.h>
#include <dt-bindings/clock/qcom,nord-gcc.h>
+#include <dt-bindings/clock/qcom,nord-gpucc.h>
#include <dt-bindings/clock/qcom,nord-negcc.h>
#include <dt-bindings/clock/qcom,nord-nwgcc.h>
#include <dt-bindings/clock/qcom,nord-segcc.h>
@@ -835,6 +839,17 @@ hscnoc: interconnect@2000000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,nord-gpucc";
+ reg = <0x0 0x03d90000 0x0 0x9800>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&nwgcc NW_GCC_GPU_GPLL0_CLK_SRC>,
+ <&nwgcc NW_GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
hpass_ag_noc: interconnect@5fc0000 {
compatible = "qcom,nord-hpass-ag-noc";
reg = <0x0 0x05fc0000 0x0 0x37080>;
@@ -877,6 +892,99 @@ nwgcc: clock-controller@8b00000 {
#power-domain-cells = <1>;
};
+ dispcc1: clock-controller@8d00000 {
+ compatible = "qcom,nord-dispcc1";
+ reg = <0x0 0x08d00000 0x0 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&nwgcc NW_GCC_DISP_1_AHB_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpu2cc: clock-controller@9890000 {
+ compatible = "qcom,nord-gpu2cc";
+ reg = <0x0 0x09890000 0x0 0xa000>;
+ clocks = <&bi_tcxo_div2>,
+ <&negcc NE_GCC_GPU_2_GPLL0_CLK_SRC>,
+ <&negcc NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@9ce0000 {
+ compatible = "qcom,nord-camcc";
+ reg = <0x0 0x09ce0000 0x0 0x20000>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ clocks = <&nwgcc NW_GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,nord-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&nwgcc NW_GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc0: clock-controller@af00000 {
+ compatible = "qcom,nord-dispcc0";
+ reg = <0x0 0x0af00000 0x0 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&nwgcc NW_GCC_DISP_0_AHB_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
tcsrcc: clock-controller@f1d9000 {
compatible = "qcom,nord-tcsrcc",
"syscon";
--
2.43.0On Sun, 20 Sep 2026 10:10:49 +0200, Shawn Guo <shengchao.guo@oss.qualcomm.com> said: > From: Taniya Das <taniya.das@oss.qualcomm.com> > > Add the GPU, camera, video, and display clock controller nodes for > the Qualcomm Nord SoC, along with their required dt-bindings includes. The last bit should be dropped? > > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> > --- Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Thanks, Bartosz
On Mon, Sep 21, 2026 at 04:49:20AM -0400, Bartosz Golaszewski wrote: > On Sun, 20 Sep 2026 10:10:49 +0200, Shawn Guo > <shengchao.guo@oss.qualcomm.com> said: > > From: Taniya Das <taniya.das@oss.qualcomm.com> > > > > Add the GPU, camera, video, and display clock controller nodes for > > the Qualcomm Nord SoC, along with their required dt-bindings includes. > > The last bit should be dropped? I think it means these lines in the patch. +#include <dt-bindings/clock/qcom,glymur-videocc.h> +#include <dt-bindings/clock/qcom,nord-camcc.h> +#include <dt-bindings/clock/qcom,nord-dispcc.h> Shawn
On Mon, 21 Sep 2026 10:53:18 +0200, Shawn Guo <shengchao.guo@oss.qualcomm.com> said: > On Mon, Sep 21, 2026 at 04:49:20AM -0400, Bartosz Golaszewski wrote: >> On Sun, 20 Sep 2026 10:10:49 +0200, Shawn Guo >> <shengchao.guo@oss.qualcomm.com> said: >> > From: Taniya Das <taniya.das@oss.qualcomm.com> >> > >> > Add the GPU, camera, video, and display clock controller nodes for >> > the Qualcomm Nord SoC, along with their required dt-bindings includes. >> >> The last bit should be dropped? > > I think it means these lines in the patch. > > +#include <dt-bindings/clock/qcom,glymur-videocc.h> > +#include <dt-bindings/clock/qcom,nord-camcc.h> > +#include <dt-bindings/clock/qcom,nord-dispcc.h> > Ah, I thought it's a leftover comment about *adding* these includes. Nevermind my comment then. Bart
On Sun, Sep 20, 2026 at 04:10:49PM +0800, Shawn Guo wrote: > From: Taniya Das <taniya.das@oss.qualcomm.com> > > Add the GPU, camera, video, and display clock controller nodes for > the Qualcomm Nord SoC, along with their required dt-bindings includes. > > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> > --- > Resend to separate from Nord display DTS series. > > Dependencies: > - Nord base DTS: https://lore.kernel.org/all/20260914031412.140856-1-shengchao.guo@oss.qualcomm.com/ The dependency is cleared, so the patch is ready to be applied. Shawn
On Mon, Sep 21, 2026 at 04:48:58PM +0800, Shawn Guo wrote: > On Sun, Sep 20, 2026 at 04:10:49PM +0800, Shawn Guo wrote: > > From: Taniya Das <taniya.das@oss.qualcomm.com> > > > > Add the GPU, camera, video, and display clock controller nodes for > > the Qualcomm Nord SoC, along with their required dt-bindings includes. > > > > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> > > --- > > Resend to separate from Nord display DTS series. > > > > Dependencies: > > - Nord base DTS: https://lore.kernel.org/all/20260914031412.140856-1-shengchao.guo@oss.qualcomm.com/ > > The dependency is cleared, so the patch is ready to be applied. Will send v2 to drop Dependencies and add review tags. Shawn
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