ARM: errata: document Cortex-A9 r4 as affected by erratum 754322

[PATCH] ARM: errata: document Cortex-A9 r4 as affected by erratum 754322

Posted by Qingfang Deng 4 days, 17 hours ago

The Cortex-A9 r4 Software Developers Errata Notice (ARM UAN 0009D),
section 2.3.3, lists erratum 754322 as affecting all r2, r3 and r4
revisions. The Kconfig help text currently mentions only r2 and r3.

Add r4p* to the affected revisions so that users configuring Cortex-A9
r4 systems know that the workaround also applies to them.

Link: https://documentation-service.arm.com/static/608118675e70d934bc69f143
Fixes: fcbdc5fe6ebe ("ARM: 6772/1: errata: possible fault MMU translations following an ASID switch")
Signed-off-by: Qingfang Deng <qingfang.deng@linux.dev>
---
 arch/arm/Kconfig | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0cc289a7184a..c7d631d5242b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -708,11 +708,12 @@ config ARM_ERRATA_754322
 	depends on CPU_V7
 	help
 	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
-	  r3p*) erratum. A speculative memory access may cause a page table walk
-	  which starts prior to an ASID switch but completes afterwards. This
-	  can populate the micro-TLB with a stale entry which may be hit with
-	  the new ASID. This workaround places two dsb instructions in the mm
-	  switching code so that no page table walks can cross the ASID switch.
+	  r3p*,r4p*) erratum. A speculative memory access may cause a page table
+	  walk which starts prior to an ASID switch but completes afterwards.
+	  This can populate the micro-TLB with a stale entry which may be hit
+	  with the new ASID. This workaround places two dsb instructions in the
+	  mm switching code so that no page table walks can cross the ASID
+	  switch.
 
 config ARM_ERRATA_754327
 	bool "ARM errata: no automatic Store Buffer drain"
-- 
2.43.0

Re: [PATCH] ARM: errata: document Cortex-A9 r4 as affected by erratum 754322

Posted by Mark Rutland 3 days, 11 hours ago

On Sun, Sep 20, 2026 at 11:29:23AM +0800, Qingfang Deng wrote:
> The Cortex-A9 r4 Software Developers Errata Notice (ARM UAN 0009D),
> section 2.3.3, lists erratum 754322 as affecting all r2, r3 and r4
> revisions. The Kconfig help text currently mentions only r2 and r3.
> 
> Add r4p* to the affected revisions so that users configuring Cortex-A9
> r4 systems know that the workaround also applies to them.
> 
> Link: https://documentation-service.arm.com/static/608118675e70d934bc69f143

The document you link to says:

	Fault Status: Present in: All r2, r3 and r4 revisions. Open

The "Open" part means this isn't fixed, and so we have no idea whether
this could afect a hypothetical r5, etc. Listing all the affected
versions is a bad idea as it wil just lead to needless churn...

> Fixes: fcbdc5fe6ebe ("ARM: 6772/1: errata: possible fault MMU translations following an ASID switch")

I don't beleive a fixes tag is necessary. The code works regardless of
what the documentation says.

> Signed-off-by: Qingfang Deng <qingfang.deng@linux.dev>
> ---
>  arch/arm/Kconfig | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 0cc289a7184a..c7d631d5242b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -708,11 +708,12 @@ config ARM_ERRATA_754322
>  	depends on CPU_V7
>  	help
>  	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
> -	  r3p*) erratum. A speculative memory access may cause a page table walk
> -	  which starts prior to an ASID switch but completes afterwards. This
> -	  can populate the micro-TLB with a stale entry which may be hit with
> -	  the new ASID. This workaround places two dsb instructions in the mm
> -	  switching code so that no page table walks can cross the ASID switch.
> +	  r3p*,r4p*) erratum. A speculative memory access may cause a page table
> +	  walk which starts prior to an ASID switch but completes afterwards.
> +	  This can populate the micro-TLB with a stale entry which may be hit
> +	  with the new ASID. This workaround places two dsb instructions in the
> +	  mm switching code so that no page table walks can cross the ASID
> +	  switch.

If you want to change this, you could say "r2p* and later", but TBH I
think we can just leave this as-is.

Mark.

>  
>  config ARM_ERRATA_754327
>  	bool "ARM errata: no automatic Store Buffer drain"
> -- 
> 2.43.0
> 
>