The DBSC5 DRAM controller protects DRAM content using inline ECC. The
current set of carveouts follows SoC documentation, which describes the
three trailing carveouts as larger than the rest.

Both the downstream IPL and mainline U-Boot on RSIP configure the ECC
carveouts to the same size for all eight carveouts. Align the carveout
sizes with the controller configuration set by the bootloader.

This makes 1638 MiB of DRAM available for each of the three carveouts,
which adds up to a total of 4915 MiB of newly accessible DRAM on this
platform with this fix.

Making this memory available does not pose a danger, since the current
set of carveouts were carefully set to a larger size to prevent any
possible issues until a confirmation from the hardware team become
available, that it is safe to apply these less restrictive settings.

Fixes: 6fa6ee724d8d ("arm64: dts: renesas: ironhide: Describe inline ECC carveouts")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
index 8e68266bb0ab0..239175c54b937 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -161,18 +161,18 @@ ecc@18cccc0000 {
 			no-map;
 		};
 
-		ecc@1a66660000 {
-			reg = <0x1a 0x66660000 0x0 0x999a0000>;
+		ecc@1acccc0000 {
+			reg = <0x1a 0xcccc0000 0x0 0x33340000>;
 			no-map;
 		};
 
-		ecc@1c66660000 {
-			reg = <0x1c 0x66660000 0x0 0x999a0000>;
+		ecc@1ccccc0000 {
+			reg = <0x1c 0xcccc0000 0x0 0x33340000>;
 			no-map;
 		};
 
-		ecc@1e66660000 {
-			reg = <0x1e 0x66660000 0x0 0x999a0000>;
+		ecc@1ecccc0000 {
+			reg = <0x1e 0xcccc0000 0x0 0x33340000>;
 			no-map;
 		};
 	};
-- 
2.53.0

On Thu, 17 Sept 2026 at 00:08, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> The DBSC5 DRAM controller protects DRAM content using inline ECC. The
> current set of carveouts follows SoC documentation, which describes the
> three trailing carveouts as larger than the rest.
>
> Both the downstream IPL and mainline U-Boot on RSIP configure the ECC
> carveouts to the same size for all eight carveouts. Align the carveout
> sizes with the controller configuration set by the bootloader.
>
> This makes 1638 MiB of DRAM available for each of the three carveouts,
> which adds up to a total of 4915 MiB of newly accessible DRAM on this
> platform with this fix.
>
> Making this memory available does not pose a danger, since the current
> set of carveouts were carefully set to a larger size to prevent any
> possible issues until a confirmation from the hardware team become
> available, that it is safe to apply these less restrictive settings.
>
> Fixes: 6fa6ee724d8d ("arm64: dts: renesas: ironhide: Describe inline ECC carveouts")
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

From the review thread on the original:
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds