This series adds support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal
NOR flash.
The part is fully described by SFDP, so patch 2 only needs the flash ID
plus a small post_bfpt fixup:
- The flash has no Status Register 2 and does not implement the 35h Read
Configuration Register command, so the core's default assumption of a
16-bit Write Status command does not hold and SNOR_F_HAS_16BIT_SR has
to be cleared.
- Its BFPT Quad Enable Requirement field carries a reserved value, which
makes spi_nor_parse_bfpt() keep the manufacturer default quad enable
method. As this is an octal-only part with no quad mode at all, the
quad_enable hook is cleared.
Patch 1 is a prerequisite: the 4BAIT parser did not pick up the 1-1-8 and
1-8-8 page program opcodes, which we need since the IS25WX01G is beyond the
3-byte address range.
Changes in v2:
- Patch 2:
* Adapt the code from 6.18 to spi-nor/next;
* Drop .name;
* Add support for flash lock/unlock.
- Link to v1: https://patch.msgid.link/20260911-mtd-spi-nor-new-issi-chip-v1-0-c54615f8c30f@analog.com
---
Nuno Sá (2):
mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 page programs from 4BAIT
mtd: spi-nor: issi: Add support for is25wx01g
drivers/mtd/spi-nor/issi.c | 25 +++++++++++++++++++++++++
drivers/mtd/spi-nor/sfdp.c | 10 ++++++++++
2 files changed, 35 insertions(+)
---
base-commit: 700bf34058ca7cd792236b1ba5caad3770d66208
change-id: 20260911-mtd-spi-nor-new-issi-chip-ef3881bab60e
--
Thanks!
- Nuno Sá