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[PATCH v5] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes

Imran Shaik posted 1 patch 2 weeks ago 
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts |  4 ++++
arch/arm64/boot/dts/qcom/shikra.dtsi        | 17 +++++++++++++++++
2 files changed, 21 insertions(+)
[PATCH v5] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
Posted by Imran Shaik 2 weeks ago 
Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core
CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support
differs across Shikra variants based on Audio subsystem enablement as
follows:
- CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets
are required to be supported on HLOS.
- CQS variant: The QAIF driver runs on the Modem, and required clocks are
handled on Modem, so from HLOS only resets are needed.
- IQS variant: no soundwire codes, hence no clocks/resets are needed.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
This patch is rebased on top of Shikra USB DT series [1] to avoid merge
conflicts, and there is no functional dependency.

[1]: https://lore.kernel.org/all/20260911-usb-shikra-v7-v8-0-851ee4bc0eec@oss.qualcomm.com/
---
Changes in v5:
- Dropped the bindings and driver patches that are already merged.
- Link to v4: https://lore.kernel.org/r/20260724-shikra-audiocorecc-v4-0-0a89bb13d817@oss.qualcomm.com

Changes in v4:
- Dropped "clk: qcom: common: Register reset controller only when resets are present" patch
  - Sashiko AI review pointed a valid GDSC-only corner case issue with this
    change, will address it in a separate patch.
  - This patch is not needed for this series, after splitting AudioCoreCC
    clocks and resets into different devices.
- Added NULL check for device_get_match_data() in driver [Sashiko AI review]
- Removed unnecessary <linux/mod_devicetable.h> include in driver [Uwe]
- Collected the R-By tags received on v2.
- Link to v3: https://lore.kernel.org/r/20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com

Changes in v3:
- Rebased on next-20260722, as the dependent RPMCC/GCC and Shikra base
  DTS changes were merged. 
- Separated the audiocorecc and audiocore_csr bindings into separate schema
  docs [Rob]
- Moved the AudioCoreCSR schema to bindings/reset/, since it now only
  describes a reset controller.
- Updated audiocorecc DTS node to use status reserved [Konrad]
- Kept audiocore_csr node globally enabled by default in DTS [Konrad]
- Collected all the R-By received on v1. 
- Link to v2: https://lore.kernel.org/r/20260708-shikra-audiocorecc-v2-0-b320d822cdd0@oss.qualcomm.com

Changes in v2:
- Separated AudioCoreCC and AudioCoreCSR nodes as both resides in two
  different register spaces. [Konrad]
- Updated bindings and driver patches to handle the separate node
  compatibles.
- Updated resets in driver patch to handle HW_CTL bit.
- Link to v1: https://lore.kernel.org/r/20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com

To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: Ajit Pandey <ajit.pandey@oss.qualcomm.com>
Cc: Imran Shaik <imran.shaik@oss.qualcomm.com>
Cc: Taniya Das <taniya.das@oss.qualcomm.com>
Cc: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts |  4 ++++
 arch/arm64/boot/dts/qcom/shikra.dtsi        | 17 +++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 286ea46d0c36..079a1636cb6a 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,10 @@ chosen {
 	};
 };
 
+&audiocorecc {
+	status = "okay";
+};
+
 &pm4125_hs_in {
 	remote-endpoint = <&usb_1_dwc3_hs>;
 };
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 1395c182a2b1..999b478e1640 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
 #include <dt-bindings/clock/qcom,shikra-gcc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
@@ -3594,6 +3595,22 @@ cti@9900000 {
 			label = "cti_apss_2";
 		};
 
+		audiocorecc: clock-controller@a0a0000 {
+			compatible = "qcom,shikra-audiocorecc";
+			reg = <0x0 0x0a0a0000 0x0 0x10000>;
+			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+				 <&sleep_clk>,
+				 <0>;
+			#clock-cells = <1>;
+			status = "reserved"; /* Owned by Modem firmware */
+		};
+
+		audiocore_csr: reset-controller@a0b4000 {
+			compatible = "qcom,shikra-audiocore-csr";
+			reg = <0x0 0x0a0b4000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
 		remoteproc_cdsp: remoteproc@b300000 {
 			compatible = "qcom,shikra-cdsp-pas";
 			reg = <0x0 0x0b300000 0x0 0x100000>;

---
base-commit: ae800ad8819a6d89308031288a6ab6789eb5d2d4
change-id: 20260605-shikra-audiocorecc-85efef073474

Best regards,
--  
Imran Shaik <imran.shaik@oss.qualcomm.com>
Re: [PATCH v5] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
Posted by Komal Bajaj 1 week, 6 days ago 
On 9/11/2026 6:06 PM, Imran Shaik wrote:
> Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core
> CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support
> differs across Shikra variants based on Audio subsystem enablement as
> follows:
> - CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets
> are required to be supported on HLOS.
> - CQS variant: The QAIF driver runs on the Modem, and required clocks are
> handled on Modem, so from HLOS only resets are needed.
> - IQS variant: no soundwire codes, hence no clocks/resets are needed.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> This patch is rebased on top of Shikra USB DT series [1] to avoid merge
> conflicts, and there is no functional dependency.
>
> [1]: https://lore.kernel.org/all/20260911-usb-shikra-v7-v8-0-851ee4bc0eec@oss.qualcomm.com/
> ---
> Changes in v5:
> - Dropped the bindings and driver patches that are already merged.
> - Link to v4: https://lore.kernel.org/r/20260724-shikra-audiocorecc-v4-0-0a89bb13d817@oss.qualcomm.com
>
> Changes in v4:
> - Dropped "clk: qcom: common: Register reset controller only when resets are present" patch
>    - Sashiko AI review pointed a valid GDSC-only corner case issue with this
>      change, will address it in a separate patch.
>    - This patch is not needed for this series, after splitting AudioCoreCC
>      clocks and resets into different devices.
> - Added NULL check for device_get_match_data() in driver [Sashiko AI review]
> - Removed unnecessary <linux/mod_devicetable.h> include in driver [Uwe]
> - Collected the R-By tags received on v2.
> - Link to v3: https://lore.kernel.org/r/20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com
>
> Changes in v3:
> - Rebased on next-20260722, as the dependent RPMCC/GCC and Shikra base
>    DTS changes were merged.
> - Separated the audiocorecc and audiocore_csr bindings into separate schema
>    docs [Rob]
> - Moved the AudioCoreCSR schema to bindings/reset/, since it now only
>    describes a reset controller.
> - Updated audiocorecc DTS node to use status reserved [Konrad]
> - Kept audiocore_csr node globally enabled by default in DTS [Konrad]
> - Collected all the R-By received on v1.
> - Link to v2: https://lore.kernel.org/r/20260708-shikra-audiocorecc-v2-0-b320d822cdd0@oss.qualcomm.com
>
> Changes in v2:
> - Separated AudioCoreCC and AudioCoreCSR nodes as both resides in two
>    different register spaces. [Konrad]
> - Updated bindings and driver patches to handle the separate node
>    compatibles.
> - Updated resets in driver patch to handle HW_CTL bit.
> - Link to v1: https://lore.kernel.org/r/20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com
>
> To: Bjorn Andersson <andersson@kernel.org>
> To: Konrad Dybcio <konradybcio@kernel.org>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> Cc: Ajit Pandey <ajit.pandey@oss.qualcomm.com>
> Cc: Imran Shaik <imran.shaik@oss.qualcomm.com>
> Cc: Taniya Das <taniya.das@oss.qualcomm.com>
> Cc: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>   arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts |  4 ++++
>   arch/arm64/boot/dts/qcom/shikra.dtsi        | 17 +++++++++++++++++
>   2 files changed, 21 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> index 286ea46d0c36..079a1636cb6a 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> @@ -23,6 +23,10 @@ chosen {
>   	};
>   };
>   
> +&audiocorecc {
> +	status = "okay";
> +};
> +
>   &pm4125_hs_in {
>   	remote-endpoint = <&usb_1_dwc3_hs>;
>   };
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 1395c182a2b1..999b478e1640 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -6,6 +6,7 @@
>   #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
>   #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
>   #include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
>   #include <dt-bindings/clock/qcom,shikra-gcc.h>
>   #include <dt-bindings/interconnect/qcom,icc.h>
>   #include <dt-bindings/interconnect/qcom,osm-l3.h>
> @@ -3594,6 +3595,22 @@ cti@9900000 {
>   			label = "cti_apss_2";
>   		};
>   
> +		audiocorecc: clock-controller@a0a0000 {
> +			compatible = "qcom,shikra-audiocorecc";
> +			reg = <0x0 0x0a0a0000 0x0 0x10000>;
> +			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> +				 <&sleep_clk>,
> +				 <0>;
> +			#clock-cells = <1>;
> +			status = "reserved"; /* Owned by Modem firmware */
> +		};
> +
> +		audiocore_csr: reset-controller@a0b4000 {
> +			compatible = "qcom,shikra-audiocore-csr";
> +			reg = <0x0 0x0a0b4000 0x0 0x1000>;
> +			#reset-cells = <1>;
> +		};
> +
>   		remoteproc_cdsp: remoteproc@b300000 {
>   			compatible = "qcom,shikra-cdsp-pas";
>   			reg = <0x0 0x0b300000 0x0 0x100000>;
>
> ---
> base-commit: ae800ad8819a6d89308031288a6ab6789eb5d2d4
> change-id: 20260605-shikra-audiocorecc-85efef073474
>
> Best regards,
> --
> Imran Shaik <imran.shaik@oss.qualcomm.com>
>

Reviewed-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Re: [PATCH v5] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
Posted by Abel Vesa 1 week, 6 days ago 
On 26-09-11 18:06:04, Imran Shaik wrote:
> Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core
> CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support
> differs across Shikra variants based on Audio subsystem enablement as
> follows:
> - CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets
> are required to be supported on HLOS.
> - CQS variant: The QAIF driver runs on the Modem, and required clocks are
> handled on Modem, so from HLOS only resets are needed.
> - IQS variant: no soundwire codes, hence no clocks/resets are needed.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

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