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[RFC][PATCH] arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes

Marek Vasut posted 1 patch 2 weeks, 1 day ago 
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 34 +++++++++++++++++------
1 file changed, 25 insertions(+), 9 deletions(-)
[RFC][PATCH] arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes
Posted by Marek Vasut 2 weeks, 1 day ago 
This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
and add msi-map into PCIe controller node.

The GIC ITS does have master interface to issue transactions to RAM.
The interface does support cacheable transactions, however, it does
not support shareable attribute, because the AXI port signals are tied
to inactive in this implementation. Therefore, add "dma-noncoherent"
DT property into the GIC ITS subnode.

The GIC redistributor does not have cacheable/shareable, therefore
add "dma-noncoherent" DT property into the GIC node.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
NOTE: I am sending this as an RFC. Den-san, would you please test
      whether this works correctly together with your Endpoint setup?
      Especially whether the Host-side MSI change does not break it?
      Thank you for your help!
---
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 34 +++++++++++++++++------
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 878b1d53fa371..e17e7732a8d3c 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -793,6 +793,8 @@ pciec0: pcie@e65d0000 {
 			resets = <&cpg 624>, <&cpg 1121>;
 			reset-names = "pwr", "core";
 			max-link-speed = <4>;
+			msi-parent = <&its 0>;
+			msi-map = <0x0 &its 0x0 0x10000>;
 			num-lanes = <2>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -803,10 +805,10 @@ pciec0: pcie@e65d0000 {
 			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
 			snps,enable-cdm-check;
 			status = "disabled";
 		};
@@ -830,6 +832,8 @@ pciec1: pcie@e65d8000 {
 			resets = <&cpg 625>, <&cpg 1122>;
 			reset-names = "pwr", "core";
 			max-link-speed = <4>;
+			msi-parent = <&its 0>;
+			msi-map = <0x0 &its 0x0 0x10000>;
 			num-lanes = <2>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -840,10 +844,10 @@ pciec1: pcie@e65d8000 {
 			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
 			snps,enable-cdm-check;
 			status = "disabled";
 		};
@@ -1290,11 +1294,23 @@ ipmmu_mm: iommu@eefc0000 {
 		gic: interrupt-controller@f1000000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
-			#address-cells = <0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
 			interrupt-controller;
 			reg = <0x0 0xf1000000 0 0x20000>,
 			      <0x0 0xf1060000 0 0x110000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			dma-noncoherent;
+
+			ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>;
+
+			its: msi-controller@40000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x40000 0x0 0x20000>;
+				dma-noncoherent;
+				msi-controller;
+				#msi-cells = <1>;
+			};
 		};
 
 		wwdt0: watchdog@ffc90000 {
-- 
2.53.0
Re: [RFC][PATCH] arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes
Posted by Geert Uytterhoeven 1 week, 4 days ago 
On Wed, 9 Sept 2026 at 19:59, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
> SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
> and add msi-map into PCIe controller node.
>
> The GIC ITS does have master interface to issue transactions to RAM.
> The interface does support cacheable transactions, however, it does
> not support shareable attribute, because the AXI port signals are tied
> to inactive in this implementation. Therefore, add "dma-noncoherent"
> DT property into the GIC ITS subnode.
>
> The GIC redistributor does not have cacheable/shareable, therefore
> add "dma-noncoherent" DT property into the GIC node.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [RFC][PATCH] arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes
Posted by Koichiro Den 2 weeks, 1 day ago 
On Wed, Sep 09, 2026 at 07:58:46PM +0200, Marek Vasut wrote:
> This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
> SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
> and add msi-map into PCIe controller node.
> 
> The GIC ITS does have master interface to issue transactions to RAM.
> The interface does support cacheable transactions, however, it does
> not support shareable attribute, because the AXI port signals are tied
> to inactive in this implementation. Therefore, add "dma-noncoherent"
> DT property into the GIC ITS subnode.
> 
> The GIC redistributor does not have cacheable/shareable, therefore
> add "dma-noncoherent" DT property into the GIC node.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Koichiro Den <den@valinux.co.jp>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> NOTE: I am sending this as an RFC. Den-san, would you please test
>       whether this works correctly together with your Endpoint setup?
>       Especially whether the Host-side MSI change does not break it?
>       Thank you for your help!

Yes, I confirmed that it works fine with renesas-next-2026-09-09-v7.3-rc1
kernel.

Tested-by: Koichiro Den <den@valinux.co.jp>

> ---
>  arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 34 +++++++++++++++++------
>  1 file changed, 25 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> index 878b1d53fa371..e17e7732a8d3c 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> @@ -793,6 +793,8 @@ pciec0: pcie@e65d0000 {
>  			resets = <&cpg 624>, <&cpg 1121>;
>  			reset-names = "pwr", "core";
>  			max-link-speed = <4>;
> +			msi-parent = <&its 0>;
> +			msi-map = <0x0 &its 0x0 0x10000>;
>  			num-lanes = <2>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> @@ -803,10 +805,10 @@ pciec0: pcie@e65d0000 {
>  			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
>  			#interrupt-cells = <1>;
>  			interrupt-map-mask = <0 0 0 7>;
> -			interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> -					<0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> -					<0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> -					<0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
>  			snps,enable-cdm-check;
>  			status = "disabled";
>  		};
> @@ -830,6 +832,8 @@ pciec1: pcie@e65d8000 {
>  			resets = <&cpg 625>, <&cpg 1122>;
>  			reset-names = "pwr", "core";
>  			max-link-speed = <4>;
> +			msi-parent = <&its 0>;
> +			msi-map = <0x0 &its 0x0 0x10000>;
>  			num-lanes = <2>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> @@ -840,10 +844,10 @@ pciec1: pcie@e65d8000 {
>  			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
>  			#interrupt-cells = <1>;
>  			interrupt-map-mask = <0 0 0 7>;
> -			interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> -					<0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> -					<0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> -					<0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
>  			snps,enable-cdm-check;
>  			status = "disabled";
>  		};
> @@ -1290,11 +1294,23 @@ ipmmu_mm: iommu@eefc0000 {
>  		gic: interrupt-controller@f1000000 {
>  			compatible = "arm,gic-v3";
>  			#interrupt-cells = <3>;
> -			#address-cells = <0>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
>  			interrupt-controller;
>  			reg = <0x0 0xf1000000 0 0x20000>,
>  			      <0x0 0xf1060000 0 0x110000>;
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			dma-noncoherent;
> +
> +			ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>;
> +
> +			its: msi-controller@40000 {
> +				compatible = "arm,gic-v3-its";
> +				reg = <0x0 0x40000 0x0 0x20000>;
> +				dma-noncoherent;
> +				msi-controller;
> +				#msi-cells = <1>;
> +			};
>  		};
>  
>  		wwdt0: watchdog@ffc90000 {
> -- 
> 2.53.0
>
Re: [RFC][PATCH] arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes
Posted by Marek Vasut 2 weeks, 1 day ago 
Hello Den-san,

On 9/10/26 10:18 AM, Koichiro Den wrote:
> On Wed, Sep 09, 2026 at 07:58:46PM +0200, Marek Vasut wrote:
>> This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
>> SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
>> and add msi-map into PCIe controller node.
>>
>> The GIC ITS does have master interface to issue transactions to RAM.
>> The interface does support cacheable transactions, however, it does
>> not support shareable attribute, because the AXI port signals are tied
>> to inactive in this implementation. Therefore, add "dma-noncoherent"
>> DT property into the GIC ITS subnode.
>>
>> The GIC redistributor does not have cacheable/shareable, therefore
>> add "dma-noncoherent" DT property into the GIC node.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
>> ---
>> Cc: Conor Dooley <conor+dt@kernel.org>
>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>> Cc: Koichiro Den <den@valinux.co.jp>
>> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
>> Cc: Magnus Damm <magnus.damm@gmail.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-renesas-soc@vger.kernel.org
>> ---
>> NOTE: I am sending this as an RFC. Den-san, would you please test
>>        whether this works correctly together with your Endpoint setup?
>>        Especially whether the Host-side MSI change does not break it?
>>        Thank you for your help!
> 
> Yes, I confirmed that it works fine with renesas-next-2026-09-09-v7.3-rc1
> kernel.
> 
> Tested-by: Koichiro Den <den@valinux.co.jp>

Thank you!

-- 
Best regards,
Marek Vasut

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