From: Peijie Shao <shaopeijie@gmail.com>
On 32-bit platforms (e.g., Zynq 7000 series), parent_rate * 1000
may overflow, leading to incorrect divisor calculation.
The issue was first found on Zynq7020 with "parent_rate=1GHz"
and "xlnx,nr-outputs=2".
Cast parent_rate to u64 and use the ULL version of DIV_ROUND*
instead.
Signed-off-by: Peijie Shao <shaopeijie@gmail.com>
---
drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index edf8c0eaca27..5abbc6b83b72 100644
--- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -881,10 +881,10 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
void __iomem *div_addr = divider->base + divider->offset;
- rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate);
+ rate_div = DIV_ROUND_DOWN_ULL((u64)parent_rate * 1000, rate);
clockout0_div = rate_div / 1000;
- pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
+ pre = DIV_ROUND_CLOSEST_ULL((u64)parent_rate * 1000, rate);
f = (u32)(pre - (clockout0_div * 1000));
f = f & WZRD_CLKOUT_FRAC_MASK;
f = f << WZRD_CLKOUT_DIVIDE_WIDTH;
--
2.43.5