On 26-09-09 08:27:22, Dinh Nguyen wrote:
> Hi Petko,
>
> On 9/9/26 06:15, Petko Manolov wrote:
> > Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
> > SoCFPGA Cyclone V” board variant. It has both (the SoC and FPGA) on the same
> > carrier and they are cross-monitoring each other.
> >
> > This is the SoCFPGA devicetree part.
> >
> > Changes in v3:
> >
> > - add Draeger AG in devicetree/bindings/vendor-prefixes.yaml
> > - separate binding changes from the actual devicetree patch
> > - remove "earlyprintk" from the boot arguments
> >
> > Petko Manolov (3):
> > Add Draeger AG as a vendor
> > Add Draeger's M48 board to the SoCFPGA family.
> > Add socfpga devicetree for Draeger's M48 board.
> >
> > .../devicetree/bindings/arm/altera.yaml | 1 +
> > .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> > arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
> > .../socfpga/socfpga_cyclone5_draeger_m48.dts | 129 ++++++++++++++++++
> > 4 files changed, 133 insertions(+)
> > create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> >
>
> Please look up what a commit header and message should look like for these
> patches. For example:
>
> patch 1/3 should look something like this:
>
> dt-bindings: vendor-prefixes: add Draeger AG
>
> Add a vendor prefix for Draegar AG, which is Draegerwerk AG & Co. KGaA
>
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
That was really dump omission on my part, sorry. Will be fixed.
> You should look what the formatting of the commit header and message look like
> for the subsystem you're submitting patches to.
>
> All of your patches are missing the appropriate formatting.
Could you please specify. I've run all of them through checkpatch.pl. Maybe
i'm missing something else?
Petko